Semiconductor integrated circuit and method of designing the same

• US 6,484,294 B1
• Filed: 01/18/2000
• Issued: 11/19/2002
• Est. Priority Date: 04/23/1999
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hotta, Takashi, Nakao, Michinobu, Kiyoshige, Yoshikazu, Hatayama, Kazumi
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/462,913
• Time in Patent Office: 1,036 Days
• Field of Search: 716/1-21, 714/30, 714/731, 714/733, 714/744, 711/101, 326/16, 326/101, 326/93, 365/201, 365/72, 327/520, 327/565
• US Class Current: 716/136
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/318583 Design for test

Abstract

A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Claims

1. A semiconductor integrated circuit comprising:

a logic circuit made of a plurality of logic elements;

a first storage element which stores data in keeping with a system clock signal for controlling said logic circuit in operation and which further stores scan data in accordance with a scan clock signal for testing said logic circuit; and

a second storage element which stores data in keeping with said system clock signal and which further stores scan data in accordance with either said system clock signal or said scan clock signal.

2. A semiconductor integrated circuit according to claim 1, wherein said second storage element selects either said system clock signal or said scan clock signal based on an externally supplied signal, said second storage element further storing the scan data in accordance with the selected clock signal.

3. A semiconductor integrated circuit according to claim 1, wherein said second storage element receives said system clock signal and said scan clock signal, selects either said system clock signal or said scan clock signal based on parameters of the two signals, and stores the scan data in keeping with the selected clock signal.

4. A semiconductor integrated circuit comprising:

a logic circuit made of a plurality of logic elements; and

a storage element which stores data in keeping with a system clock signal for controlling said logic circuit in operation and which further stores scan data either in accordance with a scan clock signal for testing said logic circuit or in keeping with said system clock signal.

5. A semiconductor integrated circuit according to claim 4, wherein said storage element receives said system clock signal and said scan clock signal, selects either said system clock signal or said scan clock signal based on parameters of the two signals, and stores the scan data in keeping with the selected clock signal.

6. A semiconductor integrated circuit comprising:

a logic circuit made of a plurality of logic elements;

a first storage element which stores data in accordance with a system clock signal for controlling said logic circuit in operation and which further stores scan data in keeping with a scan clock signal for testing said logic circuit; and

a second storage element which stores data in accordance with said system clock signal and which further stores scan data in keeping with either said system clock signal or said scan clock signal;

wherein said second storage element internally generates a switching signal for selecting either said scan clock signal or said system clock signal as the clock signal according to which the scan data are received.

7. Logic circuit data about a circuit comprising:

a logic circuit made of a plurality of logic elements;

a first storage element which stores data in accordance with a system clock signal for controlling said logic circuit in operation and which further stores scan data in keeping with a scan clock signal for testing said logic circuit; and

a second storage element which stores data in accordance with said system clock signal and which further stores scan data in keeping with either said system clock signal or said scan clock signal.