Method of generating application specific integrated circuits using a programmable hardware architecture
First Claim
Patent Images
1. A method for generating an application specific integrated circuit, the method comprising:
- a) providing a software configurable semiconductor integrated circuit having set data paths and comprising a predetermined fixed hardware architecture having a plurality of specialized task engines, each of the plurality of specialized task engines performing at least one operation comprising an algorithm, a data communication, or a data manipulation according to an instruction from at least one microtask;
b) defining a high-level language program that describes the application specific integrated circuit, the high-level language program being defined by using at least one application library that is optimized for at least one of the plurality of specialized task engines;
c) converting the high-level language program into a program image of the application specific integrated circuit; and
d) mapping the program image onto at least one of the plurality of specialized task engines to implement the application specific integrated circuit.
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Abstract
A method for generating an application specific integrated circuit including providing a software configurable semiconductor integrated circuit having a fixed hardware architecture that includes a plurality of task engines. A high-level language compiler is provided that compiles a user created high-level language program that defines the application specific integrated circuit. The compiler parses the program into a plurality of microtasks for instructing the plurality of task engines to implement the application specific integrated circuit.
38 Citations
44 Claims
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1. A method for generating an application specific integrated circuit, the method comprising:
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a) providing a software configurable semiconductor integrated circuit having set data paths and comprising a predetermined fixed hardware architecture having a plurality of specialized task engines, each of the plurality of specialized task engines performing at least one operation comprising an algorithm, a data communication, or a data manipulation according to an instruction from at least one microtask;
b) defining a high-level language program that describes the application specific integrated circuit, the high-level language program being defined by using at least one application library that is optimized for at least one of the plurality of specialized task engines;
c) converting the high-level language program into a program image of the application specific integrated circuit; and
d) mapping the program image onto at least one of the plurality of specialized task engines to implement the application specific integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
e) providing at least one of a configurable input interface and a configurable output interface;
f) providing a high-level language program that defines the at least one of the configurable input interface and the configurable output interface;
g) converting the high-level language program into a program image that includes the definition of the at least one of the configurable input interface and the configurable output interface; and
h) mapping the program image onto at least one of the plurality of specialized task engines to implement the at least one of the configurable input interface and the configurable output interface.
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3. The method of claim 2 wherein implementing the at least one of the configurable input interface and the configurable output interface comprises mapping the program image onto the at least one of the plurality of specialized task engines to implement a communication protocol for the at least one of the configurable input interface and the configurable interface.
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4. The method of claim 1 wherein the high-level language program comprises a task oriented program.
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5. The method of claim 1 wherein the high-level language program comprises an object oriented language program.
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6. The method of claim 1 wherein the high-level language program comprises a component-based program.
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7. The method of claim 1 wherein the at least one microtask comprises a Very Long Instruction Word program.
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8. The method of claim 1 further comprising loading the at least one microtask into a program memory associated with at least one of the plurality of specialized task engines.
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9. The method of claim 1 further comprising selecting an optimum task engine from the plurality of specialized task engines for performing the at least one operation according to the instruction from the at least one microtask.
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10. The method of claim 1 further comprising statically defining a schedule of multiple microtasks.
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11. The method of claim 1 further comprising inserting direct memory data references in at least one of the plurality of microtasks.
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12. The method of claim 1 wherein mapping the program image onto the at least one of the plurality of specialized task engines comprises:
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a) parsing the high-level language program into a plurality of threads; and
b) decomposing the plurality of threads into a plurality of microtasks.
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13. The method of claim 1 further comprising simulating the application specific integrated circuit prior to mapping the program image onto the at least one of the plurality of specialized task engines to implement the application specific integrated circuit.
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14. The method of claim 1 wherein the application libraries comprise Java class libraries.
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15. The method of claim 1 wherein the application libraries comprise base libraries that define a set of commonly used functions.
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16. The method of claim 1 wherein the application libraries comprise component libraries that define component objects used to build the application specific integrated circuit.
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17. The method of claim 1 wherein the application libraries comprise application framework libraries that include a complete description of the application specific integrated circuit.
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18. A software configurable semiconductor integrated circuit having a predetermined fixed hardware architecture with set data paths comprising:
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a) a plurality of specialized task engines, each of the plurality of specialized task engines performing at least one operation according to an instruction from at least one microtask, the at least one microtask being generated by a high-level language program;
b) at least one shared memory in communication with at least two of the plurality of specialized task engines, the at least one microtask being communicated to at least one of the plurality of specialized task engines through the at least one shared memory, and c) an input/output section that is in communication with at least one of the at least one shared memory. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A method for generating an application specific integrated circuit, the method comprising:
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a) providing a software configurable semiconductor integrated circuit having set data paths and comprising a predetermined fixed hardware architecture having a plurality of specialized task engines, each of the plurality of specialized task engines performing at least one operation according to an instruction from at least one microtask that is loaded into a program memory which is associated with at least one of the plurality of specialized task engines;
b) defining a high-level language program that describes the application specific integrated circuit, the high-level language program being defined by using at least one application library that is optimized for at least one of the plurality of specialized task engines;
c) converting the high-level language program into a program image of the application specific integrated circuit; and
d) mapping the program image onto at least one of the plurality of specialized task engines to implement the application specific integrated circuit. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
e) providing at least one of a configurable input interface and a configurable output interface;
f) providing a high-level language program that defines the at least one of the configurable input interface and the configurable output interface;
g) converting the high-level language program into a program image that includes the definition of the at least one of the configurable input interface and the configurable output interface; and
h) mapping the program image onto at least one of the plurality of specialized task engines to implement the at least one of the configurable input interface and the configurable output interface.
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29. The method of claim 28 wherein implementing the at least one of the configurable input interface and the configurable output interface comprises mapping the program image onto the at least one of the plurality of specialized engines to implement a communication protocol for the at least one of the configurable input interface and the configurable output interface.
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30. The method of claim 27 wherein the high-level language program comprises a task oriented program.
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31. The method of claim 27 wherein the high-level language program comprises an object oriented language program.
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32. The method of claim 27 wherein the high-level language program comprises a component-based program.
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33. The method of claim 27 wherein at least one of the plurality of specialized task engines perform an algorithm, a data communication or a data manipulation.
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34. The method of claim 27 wherein the at least one microtask comprises a Very Long Instruction Word program.
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35. The method of claim 27 further comprising selecting an optimum task engine from the plurality of specialized task engines for performing the at least one operation according to the instruction from the at least one microtask.
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36. The method of claim 27 further comprising statically defining a schedule of multiple microtasks.
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37. The method of claim 27 further comprising inserting a direct memory data reference into the at least one microtask.
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38. The method of claim 27 wherein mapping the program image onto the at least one of the plurality of specialized task engines comprises:
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e) parsing the high-level language program into a plurality of threads; and
f) decomposing the plurality of threads into a plurality of microtasks.
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39. The method of claim 27 further comprising simulating the application specific integrated circuit prior to mapping the program image onto the at least one of the plurality of specialized task engines to implement the application specific integrated circuit.
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40. The method of claim 27 wherein the application libraries comprise Java class libraries.
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41. The method of claim 27 wherein the application libraries comprise base libraries that define a set of commonly used functions.
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42. The method of claim 27 wherein the application libraries comprise component libraries that define component objects used to build the application specific integrated circuit.
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43. The method of claim 27 wherein the application libraries comprise application framework libraries that include a complete description of the application specific integrated circuit.
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44. An application specific integrated circuit comprising:
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a) means for providing a software configurable semiconductor integrated circuit having set data paths and comprising a predetermined fixed hardware architecture having a plurality of specialized task engines, each of the plurality of specialized task engines performing at least one operation comprising an algorithm, a data communication, or a data manipulation according to an instruction from at least one microtask;
b) means for defining a high-level language program that describes the application specific integrated circuit, the high-level language program being defined by using at least one application library that is optimized for at least one of the plurality of specialized task engines;
c) means for converting the high-level language program into a program image of the application specific integrated circuit; and
d) means for mapping the program image onto at least one of the plurality of specialized task engines to implement the application specific integrated circuit.
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Specification