Field programmable logic arrays with vertical transistors

• US 6,486,027 B1
• Filed: 03/08/2000
• Issued: 11/26/2002
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/520,494
• Time in Patent Office: 993 Days
• Field of Search: 438/257-267
• US Class Current: 438/259
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F² is needed per bit of logic, where F is the minimum lithographic feature size.

Claims

1. A method of forming a programmable logic array, the method comprising the steps of:

forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;

forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate;

forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;

forming a gate dielectric on at least a portion of the side surface of the pillars;

forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;

forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars;

forming an intergate dielectric, interposed between ones of the floating gates and ones of the control lines;

forming an intergate dielectric, interposed between the two control lines between the common pillars;

forming a plurality of input lines that interconnect with some of the control lines;

forming at least one first source and drain interconnection line interconnecting ones of the first source and drain regions;

forming a plurality of interconnecting array lines that interconnect from the second source and drain regions corresponding to the control lines having connection with the input lines to the control lines not connected to the input lines; and

forming a plurality of output lines, each output line interconnecting with the second source and drain regions not connected to the interconnecting array lines.

2. The method of claim 1, further comprising the step of forming an insulating layer between the semiconductor pillars and a semiconductor portion of the substrate.

8. The method of claim 1, wherein the step of forming the plurality of second source and drain regions comprises the step of ion-implanting a dopant of the second conductivity type.

9. The method of claim 1, wherein the step of forming the gate dielectric comprises the step of growing on the side surface of each pillar a layer of silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers.

10. The method of claim 1, wherein the step of forming the plurality of interconnecting array lines comprises the steps of:

depositing an insulator over the pillars, the floating gates and the control lines, and first and second input lines;

forming contact holes in the insulator to contact the second and source drain regions of each pillar;

depositing a conductive layer on the insulator and in the contact holes; and

etching the conductive layer to form the resulting interconnecting array lines.

11. The method of claim 1, wherein the step of forming the plurality of output lines comprises the steps of:

depositing an insulator over the pillars, the floating gates and the control lines, and first and second input lines;

forming contact holes in the insulator to contact the second source and drain regions of each pillar;

depositing a conductive layer on the insulator and in the contact holes; and

etching the conductive layer to form the resulting output lines.

3. A method of forming a programmable logic array, the method comprising the steps of:

forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;

forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate;

forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;

forming a gate dielectric on at least a portion of the side surface of the pillars;

forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;

forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars;

forming an intergate dielectric, interposed between ones of the floating gates and ones of the control lines;

forming an intergate dielectric, interposed between the two control lines between the common pillars;

forming a plurality of input lines that interconnect with some of the control lines;

forming at least one first source and drain interconnection line interconnecting ones of the first source and drain regions;

forming a plurality of interconnecting array lines that interconnect from the second source and drain regions corresponding to the control lines having connection with the input lines to the control lines not connected to the input lines; and

forming a plurality of output lines, each output line interconnecting with the second source and drain regions not connected to the interconnecting array lines;

wherein the step of forming the at least one first source and drain interconnection line is carried out at least partially within the substrate.

4. The method of claim 3, wherein the step of forming the plurality of input lines includes forming a plurality of substantially parallel input lines.

5. A method of forming a programmable logic array, the method comprising the steps of:

forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;

forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate;

forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;

forming a gate dielectric on at least a portion of the side surface of the pillars;

forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;

forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars;

forming an intergate dielectric, interposed between ones of the floating gates and ones of the control lines;

forming an intergate dielectric, interposed between the two control lines between the common pillars;

forming a plurality of input lines that interconnect with some of the control lines;

forming at least one first source and drain interconnection line interconnecting ones of the first source and drain regions;

forming a plurality of interconnecting array lines that interconnect from the second source and drain regions corresponding to the control lines having connection with the input lines to the control lines not connected to the input lines; and

forming a plurality of output lines, each output line interconnecting with the second source and drain regions not connected to the interconnecting array lines;

wherein the step of forming the plurality of pillars further comprises the steps of;

growing an epitaxial layer on the substrate;

etching the epitaxial layer and a portion of the underlying substrate to form a plurality of first troughs therein for carrying an insulator; and

etching the epitaxial layer to form therein a plurality of second troughs, substantially orthogonal to the plurality of first troughs, the second troughs for carrying the input lines.

6. The method of claim 5, wherein the step of forming the plurality of floating gates comprises the steps of:

depositing polysilicon in the second troughs; and

etching the deposited polysilicon in a median portion of the second troughs to form ones of the floating gates on either side of the second troughs, each floating gate adjacent to one of the pillars but separated therefrom by the gate dielectric.

7. The method of claim 6, wherein the steps of forming the plurality of input lines comprises the steps of:

etching into the substrate in a median portion of the second troughs; and

depositing conductive polysilicon in and above the substrate in the etched median portion of the second troughs to form the input lines.

12. A method of forming a programmable logic array on a substrate, the method comprising the steps of:

forming an AND plane and an OR plane, comprising;

forming a first source and drain layer at a surface of the substrate;

forming a semiconductor epitaxial layer on the first source and drain layer;

forming a second source and drain layer at a surface of the epitaxial layer;

etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;

forming an insulator in the first troughs;

etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;

forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;

forming a conductive layer in the second troughs;

removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;

forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; and

forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.

13. The method of claim 12, wherein the substrate is a bulk semiconductor.

14. The method of claim 12, wherein the substrate includes a semiconductor-on-insulator portion.

15. The method of claim 12, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.

16. A method of forming a programmable logic array on a substrate, the method comprising the steps of:

forming an AND plane and an OR plane, comprising;

forming a first source and drain layer at a surface of the substrate;

forming a semiconductor epitaxial layer on the first source and drain layer;

forming a second source and drain layer at a surface of the epitaxial layer;

etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;

forming an insulator in the first troughs;

etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;

forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;

forming a conductive layer in the second troughs;

removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;

forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;

forming split control line regions between opposing floating gate regions in the second troughs;

separating from the floating gate regions in the second troughs by the intergate dielectric layer;

separating the split control lines by the intergate dielectric layer.

17. The method of claim 16, wherein the substrate is a bulk semiconductor.

18. The method of claim 16, wherein the substrate includes a semiconductor-on-insulator portion.

19. The method of claim 16, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.

20. A method of forming a programmable logic array on a substrate, the method comprising the steps of:

forming an AND plane and an OR plane, comprising;

forming a first source and drain layer at a surface of the substrate;

forming a semiconductor epitaxial layer on the first source and drain layer;

forming a second source and drain layer at a surface of the epitaxial layer;

etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;

forming an insulator in the first troughs;

etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;

forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;

forming a conductive layer in the second troughs;

removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;

forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;

forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer; and

forming an inverter in communication with the AND plane and the OR plane; and

forming a driver in communication with the AND plane and the OR plane.

21. The method of claim 20, wherein the substrate is a bulk semiconductor.

22. The method of claim 20, wherein the substrate includes a semiconductor-on-insulator portion.

23. The method of claim 20, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.

24. A method of forming a programmable logic array on a substrate, the method comprising the steps of:

forming an AND plane and an OR plane, comprising;

forming a first source and drain layer at a surface of the substrate;

forming a semiconductor epitaxial layer on the first source and drain layer;

forming a second source and drain layer at a surface of the epitaxial layer;

etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;

forming an insulator in the first troughs;

etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;

forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;

forming a conductive layer in the second troughs;

removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;

forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;

forming split control line regions between opposing floating gate regions in the second troughs;

separating from the floating gate regions in the second troughs by the intergate dielectric layer;

separating the split control lines by the intergate dielectric layer;

forming an inverter in communication with the AND plane and the OR plane; and

forming a driver in communication with the AND plane and the OR plane.

25. The method of claim 24, wherein the substrate is a bulk semiconductor.

26. The method of claim 24, wherein the substrate includes a semiconductor-on-insulator portion.

27. The method of claim 24, further comprising forming an insulating layer undercutting semiconductor regions between the first troughs.