Active pixel sensor array with electronic shuttering

• US 6,486,503 B1
• Filed: 01/22/1997
• Issued: 11/26/2002
• Est. Priority Date: 01/28/1994
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Kang, Donghee
• Application Number:
  US08/787,778
• Time in Patent Office: 2,134 Days
• Field of Search: 377/60, 257/239, 257/292, 257/294, 257/229
• US Class Current: 257/215
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/10 for transforming different wavelengths into image signals
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An active pixel cell includes electronic shuttering capability. The cell can be “shuttered” to prevent additional charge accumulation. One mode transfers the current charge to a storage node that is blocked against accumulation of optical radiation. The charge is sampled from a floating node. Since the charge is stored, the node can be sampled at the beginning and the end of every cycle. Another aspect allows charge to spill out of the well whenever the charge amount gets higher than some amount, thereby providing anti blooming.

Claims

1. An optical device, comprising:

a substrate of a semiconductor material;

a light collection area, formed in said substrate, and comprising a photogate and a first optical storage area which is controlled by said photogate, said first optical storage area operating to accumulate optical charge under control of said photogate;

a supplemental charge storage area formed in said substrate, physically separated from said first optical storage area and disposed adjacent to said light collection area;

a charge transfer mechanism formed in said substrate and coupled between said first optical storage area and said supplemental charge storage area, said charge transfer mechanism being selectively actuated to allow transfer of charge in said first optical storage area to said supplemental charge storage area;

a floating output node formed on said substrate and connected to selectively receive charge from said supplemental charge storage area;

a transfer element which transfers charge from said supplemental charge storage area to said floating output node; and

a correlated double sampling element, comprising a first element, operating to sample a voltage on said floating output node prior to transfer of charge thereto, and a second element operating to sample a voltage on said floating output node after transfer of charge thereto.

2. A device as in claim 1 wherein said light collection area has a first area, said supplemental charge storage area has a second area smaller than said first area.

3. A device as in claim 1 wherein said light collection area has a first area, said supplemental charge storage area has a second area that is substantially the same as said first area.

4. A device as in claim 1 further comprising a control element, said control element provides a potential on the photogate which is initially lower than a potential on the charge transfer mechanism to allow charge to be accumulated therein.

5. A device as in claim 1, further comprising an optical shield, optically covering at least a portion of the supplemental charge storage area.

6. A device as in claim 5 further comprising a microlens overlying the optical shield, and refracting at least a portion of the light impinging over an area of the optical shield to the light collection area.

7. A device as in claim 1, wherein said charge transfer mechanism is a gate and at least part of the gate forming said charge transfer mechanism overlaps with the photogate.

8. A device as in claim 7, wherein said overlapping gates are formed using a double poly process.

9. An optical pixel cell device comprising:

a substrate;

a plurality of pixel areas formed on said substrate, each pixel area comprising;

a) an optical blocking layer located adjacent said substrate, dividing each said pixel into an optically blocked area, and an optically unblocked area;

b) a charge accumulating device, located in said optically unblocked area;

c) a charge storage device located in said optically blocked area to receive and store charge from said charge accumulating device;

d) a readout circuit formed of MOS, integrated on said substrate and connected to said charge storage device, said readout circuit having a selection transistor that selects the pixel, a sensing MOS transistor that buffers a signal from said charge storage device and converts it into an output electrical signal and a correlated double sampling element that samples values before and after accumulation of charge;

e) a charge sink adjacent to said charge accumulating device and operable to receive a certain amount of charge from said charge accumulating device so as to prevent said certain amount of charge from being coupled to said charge storage device; and

f) a transferring element disposed relative to said charge sink and said charge accumulating device and configured to control transfer of charge from said charge accumulating device to said charge sink, said transferring element set at a potential to prevent charge accumulated in said charge accumulating device in excess of a maximum level from being coupled into said storage device; and

a control circuit to set charge accumulating devices in said pixel areas to simultaneously accumulate charge of an input scene over during an integration period and to initiate another integration in each of said pixel areas after accumulated charge in each charge accumulating device at an end of said integration period is transferred into a respective charge storage device,

wherein said control circuit controls said readout circuit, during said another integration, to read outputs from charge storage devices in said pixel areas at different times to form a snapshot image captured simultaneously by different pixels during said integration period.

10. A device as in claim 9 wherein said charge accumulating device includes a controlling gate, and further comprising a control device which biases a gate on the charge accumulating device to a first level which allows said charge accumulation device to collect light, and prevents said light from passing into said blocked area, and then to a second level which allows light to pass to said blocked area.

11. A device as in claim 9, wherein said sensing MOS transistor has a floating diffusion producing said output electrical signal and further comprising a transfer gate, connected to transfer charge from said charge storage device to said floating diffusion.

12. A device as in claim 9, further comprising a lens element layer, formed as a layer overlying at least a portion of said optically blocked layer, and which refracts light from said optically blocked layer to said optically unblocked layer.

13. A device as in claim 9, wherein said charge accumulation device includes a photogate with a charge storage area, and said transferring element overlaps said photogate.

14. An active pixel sensor system, comprising:

a substrate with a light collection area including a light collecting photogate well and a photogate which selects whether said light collecting photogate well receives charge or not, dependent on a state of an applied voltage thereto;

a shutter element form on said substrate adjacent to said light collecting photogate well, responding to a shutter control signal at a first value to prevent accumulation of charge in said light collection area and to said shutter control signal at a second value to permit accumulation of charge in said light collection area;

a floating sensing element formed on said substrate to receive charge from said light collecting photogate well, and a gate which selectively provides charge from said light collecting photogate well to said floating sensing element;

a control circuit that produces said shutter control signal, controlling said photogate, and said gate and said shutter element, such that a charge on said floating sensing element is sampled at a beginning of a first period of integration, and a charge on said floating sensing element is sampled at an end of the same first period of integration, and said shutter element is turned on to prevent said accumulation of charge at least at one of said beginning and end of said first period;

a circuit which correlates said beginning and said end samples to form a correlated measurement indicating a different between said beginning and said end samples; and

a storage well and a storage transfer element formed adjacent to said light collecting photogate well on said substrate, wherein a voltage is applied to said storage well at an end of an integration period to transfer charge from said light collecting photogate well to said storage well, and wherein charge is not transferred from said storage well to said floating element until after said beginning sample taken at said beginning of said first period of integration.

15. A sensor as in claim 14 further comprising an optical blocking element, covering at least said storage well.

16. A system as in claim 14, wherein said gate and said photogate overlap with one another.

17. An active pixel sensor with shuttering and correlated double sampling, comprising:

a photogate well including a photogate which controls application of charge into said photogate well, a charge shutter which selectively removes charge from said photogate when biased to a predetermined potential, a floating sampling point, a transfer gate which transfers charge from said photogate well to said floating sampling point, and a control circuit, controlling said transfer of charge, said control circuit also including a first sampling element which samples said floating sampling point at a beginning of a cycle, prior to transferring charge to said floating sampling point, and a second sampling element, which samples said floating sampling point at the end of a cycle, subsequent to transferring charge accumulated during a charge accumulation cycle.

18. An active pixel sensor as in claim 17 further comprising a storage well including a storage gate, and a second transfer gate, connecting said storage well to said photogate well, an output transfer gate connected to said storage well, and wherein said control circuit controls said charge shutter to remain on during a time of charge collection, then to turn off, subsequently controls said second transfer gate to transfer charge from said photogate well to said charge storage well, and subsequently, after said sampling at the beginning of the cycle, transferring said charge from said storage well to said floating sampling point.

19. An active pixel sensor as in claim 18 further comprising an optical light shielding layer, covering said storage well.

20. An active pixel sensor as in claim 17 wherein said shutter comprises a charge sink, and a charge sink transfer gate coupled between said photogate well and said charge sink, said transfer gate set at a first potential level to allow charge to accumulate in said photogate well and set at a second level to prevent charge from accumulating in said photogate well, and wherein said first potential level on said sink transfer gate is set lower than a level necessary to allow output to provide an anti-blooming control.

21. An active pixel sensor array, comprising:

a substrate having a plurality of chip areas defining pixels, each said pixel including a photogate having a photogate electrode defining a light collection area having an optically exposed surface which is exposed to incoming optical radiation and a first charge storage area, and each pixel area also including an optically shielded area that has an optical shield to shield against incoming optical radiation, said optically shielded area including a second charge storage area operating to store charge accumulated during a previous charge cycle, a transfer gate transferring charge that has accumulated from said first charge storage area to said second charge storage area, a floating node, a second transfer gate operable to transfer charge from said second charge storage area to said floating node, correlated double sampling circuitry that samples a potential of said floating node prior to transfer of charge, and again subsequent to said accumulation of charge and determines a difference therebetween, and a control circuit to read output signals of said pixels at different times indicative of charge in said second charge storage areas to represent a snapshot of an input scene from charge accumulated in said first charge storate areas in the previous charge cycle, while said first charge storage areas are accumulating new charge.

22. An array as in claim 21 further comprising an optical sink, and a sink transfer gate, selectively transferring charge to said optical sink;

said transfer gate biased to a level lower than a bias on said second light transfer mechanism.

23. An array as in claim 21, wherein said photogate electrode and said transfer gate overlap at least partly with one another.

24. A method of operating an active pixel sensor, comprising:

defining a beginning of an integration period and an end of an integration period during which integration period charge is to be accumulated;

accumulating charge in multiple photocollectors beginning at the beginning of the integration period to store incoming charge into a photogate storage well of multiple elements within the active pixel sensor;

only at the end of the integration period, transferring accumulated charge from each said photocollector to an associated storage well separated from said photogate storage well;

sampling a value of first floating nodes;

transferring the charge from the storage wells to said floating nodes at times that are subsequent to times when said first floating nodes are first sampled; and

after transferring the charge, sampling a value on said floating nodes again to obtain a correlated value indicating an amount of charge accumulated on the floating nodes.

25. A method as in claim 24 further comprising setting a first potential level of a gate adjacent to said photogate storage well to a selected first value to remove charge in excess of a maximum level from the photogate storage well to a charge sink so as to provide an anti-blooming control during the integration period.

26. A method of operating an active pixel sensor comprising:

accumulating charge in an array of pixels at a same time over an integration period by;

biasing a photogate well to a first potential level to allow charge to accumulate therein;

biasing an output gate, connected to said photogate well, to a second potential level higher than said first potential level to prevent charge from passing out of said photogate well via said output gate while charge is accumulating;

determining a level of desired charge accumulation in said photogate well;

biasing a charge sink to a third potential level which is higher than said level of said photogate well by an amount related to said amount of desired charge accumulation, but lower than a level of bias of said output gate, to prevent charge accumulation beyond said desired amount from spilling past said output gate;

controlling said output gate for each photogate at an end of said integration period to transfer accumulated charge to an adjacent storage well in each pixel;

buffering and selecting an output signal, within each pixel;

initiating another integration in photogate wells in said pixels after said transfer;

double sampling said output signal, within each pixel, to produce an output indicating only the incoming charge amounts; and

reading output signals from said pixels at different times, during said another integration, to form a snapshot of an input scene captured during said integration period.

27. A method as in claim 26 further comprising providing a shutter operation by lowering said third potential level to a value less than the first potential in said photogate well, thereby causing charge in said photogate well to spill into said charge sink.

28. An imaging device comprising:

a monolithic semiconductor integrated circuit substrate;

a focal plane array of pixel cells, each of said pixel cells comprising;

a photogate, overlying said substrate, and capable of accumulating photo-generated charge in an underlying portion of said substrate during an integration cycle,

a supplemental charge storage well formed adjacent to said underlying portion under said photogate and coupled to receive and store charge accumulated in said underlying portion in a previous integration cycle preceding said integration cycle

a charge coupled device section formed on said substrate adjacent said supplemental charge storage well and having a floating sensing node which produces a signal indicative of charge in said supplemental charge storage well,

an electronic shutter formed on said substrate adjacent said photogate and capable of draining charge from said underlying portion of the substrate;

a plurality of readout circuits formed on said substrate, each coupled to receive said signal from said floating sensing node of at least one pixel and including a double sampling circuit element which samples a potential of said floating node prior to and subsequent to a transfer of charge from said underlying portion to said supplemental charge storage well to produce a differential output signal; and

a control circuit to read differential output signals of said pixels at different times to represent an input image captured simultaneously by said pixels in said previous integration cycle, while underlying portions in said pixels are accumulating new charge.

29. The imaging device of claim 28, wherein each of said pixel cells further comprises:

a drain diffusion connected to a drain bias voltage.

30. The imaging device of claim 29, wherein said electronic shutter comprises:

said drain diffusion; and

a shutter gate between said photogate and said drain diffusion.

31. The imaging device of claim 28, wherein said electronic shutter comprises:

a shutter drain diffusion connected to a shutter drain bias voltage; and

a shutter gate between said photogate and said shutter drain diffusion.

32. The imaging device of claim 28, wherein:

said photogate is connected to a photogate bias voltage;

said transfer gate is connected to a transfer gate bias voltage;

said electronic shutter comprises,

a shutter drain diffusion connected to a shutter drain bias voltage, and

a shutter gate between said photogate and said shutter drain diffusion; and

in a closed shutter mode, where the shutter drain bias voltage is greater than the photogate bias voltage which is in turn greater than the transfer gate bias voltage, the electronic shutter drains charge from said underlying portion of the substrate.

33. The imaging device of claim 32, wherein:

in an integrating mode, where the photogate bias voltage is greater than the shutter drain bias voltage, charge accumulates in said underlying portion of said substrate.

34. The imaging device of claim 33, wherein:

in the integrating mode, the shutter drain bias voltage is greater than the transfer gate bias voltage, thereby providing anti-blooming control.

35. The imaging device of claim 33, wherein:

in a charge transfer mode, where the shutter drain bias voltage is smaller than the transfer gate bias voltage and the photogate bias voltage is pulsed to a smaller voltage than the transfer gate bias voltage, charge is transferred form said underlying portion of said substrate to said sensing node.

36. The imaging device of claim 28, wherein a first gap exists between the photogate and the charge coupled device section and a second gap exists between the photogate and the electronic shutter, the imaging device further comprising:

a first floating diffusion underlying the first gap; and

,

a second floating diffusion underlying the second gap.

37. An imaging device, comprising a monolithic semiconductor integrated circuit substrate and a focal plane array of pixel cells formed on said substrate, each of said pixel cells comprising:

a photogate, overlying said substrate, and capable of accumulating photo-generated charge in an underlying portion of said substrate,

a readout circuit,

a charge coupled device section formed on said substrate adjacent said photogate having a sensing node connected to said readout circuit and at least one charge coupled device stage capable of transferring charge from said underlying portion of the substrate to said sensing node, and

an electronic shutter formed on said substrate adjacent said photogate and capable of draining charge from said underlying portion of the substrate, said electronic shutter having a shutter drain diffusion connected to a shutter drain bias voltage and a shutter gate between said photogate and said shutter drain diffusion,

a drain diffusion connected to a drain bias voltage; and

a reset gate between said floating node and said drain diffusion; and

wherein,

the shutter drain diffusion is the drain diffusion of an adjacent pixel cell.

38. An imaging device, comprising a monolithic semiconductor integrated circuit substrate and a focal plane array of pixel cells formed in said substrate, each of said pixel cells comprising:

a photogate, overlying said substrate, and capable of accumulating photo-generated charge in an underlying portion of said substrate,

a readout circuit,

a charge coupled device section formed on said substrate adjacent said photogate having a sensing node connected to said readout circuit and at least one charge coupled device stage capable of transferring charge from said underlying portion of the substrate to said sensing node, and

an electronic shutter formed on said substrate adjacent said photogate and capable of draining charge from said underlying portion of the substrate,

wherein a first gap exists between the photogate and the charge coupled device section and a second gap exists between the photogate and the electronic shutter, and wherein the photogate further comprises;

a first overlying section which overlies the first gap; and

,

a second overlying section which overlies the second gap.

39. An anti-blooming active pixel device, comprising:

a substrate;

a charge collecting area in said substrate, said charge collecting area including a controlling element which controls accumulation of charge in said charge collection area, according to an applied bias;

a charge sink area, separated from said charge collecting area;

a first transfer element, coupled between said charge collecting area and said charge sink area, said first transfer element transferring charge when biased to a level lower in potential than a potential of the bias on said controlling element;

wherein said first transfer element is biased to a first level to remove charge from said charge collecting area, and biased to a second level to allow charge to collect in said charge collecting area, said second level being a level which is lower than a maximum level which would allow all charge to collect in said charge collecting area to prevent blooming; and

a readout circuit formed of MOS, integrated on said substrate and connected to said charge storage device, said readout circuit having a selection transistor that selects the pixel, a sensing MOS transistor that buffers a signal from said charge storage device and converts it into an output electrical signal and a correlated double sampling element that samples values before and after accumulation of charge.

40. A device as in claim 39 further comprising a floating element, a charge detection device, and a second transfer element connected between said light collecting area and said floating element, said second transfer element selectively biased between a first level which blocks charge in said charge collecting area from transferring to said floating element, and a second level which allows charge in said charge collecting area to transfer to said floating element, wherein a level of bias on said second transfer element is a higher potential then a level of bias on said transfer element while charge is being accumulated to prevent excess charge from spilling into said floating element.

41. A device as in claim 40, further comprising a charge storage area, coupled between said charge collecting area and said floating element.

42. A device as in claim 41, further comprising:

a lens element layer, formed as a layer overlying at least a portion of said optically blocked layer, and which refracts light from said optically blocked layer to said optically unblocked layer.

43. A method of operating an active pixel sensor, comprising:

defining a beginning of an integration period and an end of an integration period during which charge is to be accumulated simultaneously in multiple photocollectors in response to an input scence;

accumulating charge in each of said multiple photocollectors beginning at the beginning of the integration period to store incoming charge into a photogate well of multiple elements within the active pixel sensor;

at the end of the integration period, transferring accumulated charge from each photocollector to an associated storage well while initiating another integration period in each photocollector;

sampling a value of a first floating node, associated with a first storage well coupled to a first photocollector, at a first time;

sampling a value of a second floating node, associated with a second storage well coupled to a second photocollector, at a second time subsequent to said first time; and

using said values obtained from said first and second floating nodes to image the same scene.

44. A method as in claim 43 further comprising providing an anti-blooming control during the integration period.

45. A method as in claim 44 wherein said anti-blooming control comprises biasing a first gate which is connected to a sink to a level lower than said first level.