Semiconductor module with encapsulant base

• US 6,486,549 B1
• Filed: 11/10/2001
• Issued: 11/26/2002
• Est. Priority Date: 11/10/2001
• Status: Expired due to Fees

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Chiang, Cheng-Lien
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US10/052,810
• Time in Patent Office: 381 Days
• Field of Search: 257/723, 257/687, 257/693, 257/698, 257/778, 257/797
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor module includes a first semiconductor chip assembly, a second semiconductor chip assembly, an encapsulant base and an electrical interconnect. The first assembly includes a first semiconductor chip, a first conductive trace and a first connection joint, the first chip includes a first conductive pad, the first trace extends within and outside a periphery of the first chip, and the first connection joint contacts and electrically connects the first trace and the first pad. The second assembly includes a second semiconductor chip, a second conductive trace and a second connection joint, the second chip includes a second conductive pad, the second trace extends within and outside a periphery of the second chip, and the second connection joint contacts and electrically connects the second trace and the second pad. The encapsulant base is disposed between and in contact with the first and second chips and the first and second traces. The electrical interconnect contacts the first and second traces in a through-hole that extends through the encapsulant base and is located outside the peripheries of the first and second chips, thereby electrically connecting the first and second traces.

Claims

1. A method of making a semiconductor module, comprising:

providing a first semiconductor chip assembly that includes a first semiconductor chip and a first carrier, wherein the first chip includes a first conductive pad and the first carrier includes a first conductive trace;

providing a second semiconductor chip assembly that includes a second semiconductor chip and a second carrier, wherein the second chip includes a second conductive pad and the second carrier includes a second conductive trace;

forming an encapsulant base between and in contact with the first and second assemblies;

forming a through-hole that extends through the carriers and the encapsulant base and is located outside the peripheries of the first and second chips;

forming an electrical interconnect in the through-hole that contacts the first and second traces in the through-hole; and

forming first and second connection joints, wherein the first connection joint contacts and electrically connects the first trace and the first pad, and the second connection joint contacts and electrically connects the second trace and the second pad.

2. The method of claim 1, wherein forming the encapsulant base includes contacting the encapsulant base to the first and second chips and the first and second traces.

3. The method of claim 1, wherein forming the encapsulant base includes transfer molding the encapsulant base.

4. The method of claim 1, wherein forming the through-hole includes mechanically drilling the through-hole through the carriers and the encapsulant base.

5. The method of claim 1, wherein forming the electrical interconnect includes electrolessly plating a metal on sidewalls of the through-hole.

6. The method of claim 1, including forming the connection joints after forming the electrical interconnect.

7. The method of claim 1, including forming an attachment joint that mechanically attaches the first and second carriers to one another before forming the encapsulant base.

8. The method of claim 7, including removing the attachment joint after forming the encapsulant base.

9. The method of claim 1, including performing the steps after providing the assemblies in the sequence set forth.

10. The method of claim 1, wherein the module is devoid of wire bonds, TAB leads and solder joints.

11. A method of making a semiconductor module, comprising:

providing a first semiconductor chip assembly that includes a first semiconductor chip and a first carrier, wherein the first chip includes a first conductive pad and the first carrier includes a first conductive trace;

providing a second semiconductor chip assembly that includes a second semiconductor chip and a second carrier, wherein the second chip includes a second conductive pad and the second carrier includes a second conductive trace;

forming an attachment joint that mechanically attaches the first and second carriers;

forming an encapsulant base between and in contact with the first and second assemblies after forming the attachment joint;

forming a through-hole that. extends through the carriers and the encapsulant base and is located outside the peripheries of the first and second chips;

forming an electrical interconnect in the through-hole that contacts the first and second traces in the through hole;

forming first and second connection joints, wherein the first connection joint contacts and electrically connects the first trace and the first pad, and the second connection joint contacts and electrically connects the second trace and the second pad; and

removing the attachment joint.

12. The method of claim 11, wherein forming the attachment joint includes welding the first and second carriers to one another.

13. The method of claim 11, wherein forming the encapsulant base includes contacting the encapsulant base to the first and second chips and the first and second traces.

14. The method of claim 11, wherein forming the encapsulant base includes transfer molding the encapsulant base.

15. The method of claim 11, wherein forming the through-hole includes mechanically drilling the through-hole through the carriers and the encapsulant base.

16. The method of claim 11, wherein forming the electrical interconnect includes electrolessly plating a metal on sidewalls of the through-hole.

17. The method of claim 11, including forming the connection joints after forming the electrical interconnect.

18. The method of claim 11, including bending the first carrier to form a pair of legs that extend across a thickness of the first chip, and then forming the attachment joint between the legs and the second carrier.

19. The method of claim 11, including performing the steps after providing the assemblies in the sequence set forth.

20. The method of claim 11, wherein the module is devoid of wire bonds, TAB leads and solder joints.

21. A method of making a semiconductor module, comprising the following steps in the sequence set forth:

providing first and second semiconductor chip assemblies, wherein the first assembly includes a first semiconductor chip and a first carrier, the first chip includes a first top surface and a first bottom surface, the first top surface includes a first conductive pad, the first carrier includes a first metal base and a first conductive trace, the first top surface faces towards the first metal base, the second assembly includes a second semiconductor chip and a second carrier, the second chip includes a second top surface and a second bottom surface, the second top surface includes a second conductive pad, the second carrier includes a second metal base and a second conductive trace, and the second top surface faces towards the second metal base;

forming an attachment joint that mechanically attaches the first and second carriers, wherein the first and second traces are exposed and face towards one another, and the first and second bottom surfaces are exposed and face towards one another;

forming an encapsulant base between and in contact with the first and second traces and the first and second bottom surfaces;

forming a through-hole that extends through the first and second metal bases and the encapsulant base and exposes the first and second traces and is located outside the peripheries of the first and second chips;

forming an electrical interconnect in the through-hole that contacts the first and second traces in the through-hole;

forming first and second connection joints, wherein the first connection joint contacts and electrically connects the first trace and the first pad, and the second connection joint contacts and electrically connects the second trace and the second pad; and

removing the attachment joint.

22. The method of claim 21, wherein forming the attachment joint includes welding the first and second carriers to one another.

23. The method of claim 21, wherein forming the encapsulant base includes transfer molding the encapsulant base.

24. The method of claim 21, wherein forming the through-hole includes mechanically drilling the through-hole through the first and second metal bases, the first and second traces and the encapsulant base.

25. The method of claim 21, wherein forming the electrical interconnect includes electrolessly plating a metal on sidewalls of the first and second metal bases, the first and second traces and the encapsulant base.

26. The method of claim 21, including electroplating the first trace on the first metal base, and electroplating the second trace on the second metal base.

27. The method of claim 21, including bending the first metal base to form a pair of legs that extend across a thickness of the first chip, then positioning the carriers such that the legs across a thickness of the second chip and contact the second metal base, and then forming the attachment joint between the legs and the second metal base.

28. The method of claim 21, including etching the first metal base to expose the first trace and etching the second metal base to expose the second trace after forming the electrical interconnect.

29. The method of claim 21, wherein the module is a dual in-line memory module.

30. The method of claim 21, wherein the module is devoid of wire bonds, TAB leads and solder joints.

31. A method of making a semiconductor module, comprising;

providing a first semiconductor chip that includes a first conductive pad;

providing a first metal base;

electroplating a first conductive trace on the first metal base;

disposing a first insulative adhesive between the first chip and the first metal base, thereby mechanically attaching the first chip to the first metal base;

providing a second semiconductor chip that includes a second conductive pad;

providing a second metal base;

electroplating a second conductive trace on the second metal base;

disposing a second insulative adhesive between the second chip and the second metal base, thereby mechanically attaching the second chip to the second metal base; and

then, in the sequence set forth,

forming an attachment joint that mechanically attaches the first and second metal bases;

forming an encapsulant base that contacts the first and second metal bases and the first and second traces;

forming a through-hole that extends through the first and second metal bases and the encapsulant base and exposes the first and second traces and is located outside the peripheries of the first and second chips; and

forming an electrical interconnect in the through-hole that contacts the first and second traces in the through-hole, wherein a first connection joint contacts and electrically connects the first trace and the first pad, and a second connection joint contacts and electrically connects the second trace and the second pad, such that the first and second pads are electrically connected to one another by an electrically conductive path that includes the first and second traces, the first and second connection joints and the electrical interconnect.

32. The method of claim 31, wherein forming the attachment joint includes welding the first and second metal bases to one another.

33. The method of claim 31, wherein forming the encapsulant base includes contacting the encapsulant base to the first and second chips on surfaces opposite the first and second pads.

34. The method of claim 31, wherein forming the encapsulant base includes transfer molding the encapsulant base.

35. The method of claim 31, wherein forming the through-hole includes mechanically drilling the through-hole through the first and second metal bases, the first and second traces and the encapsulant base.

36. The method of claim 31, wherein forming the electrical interconnect includes electrolessly plating a first metal on,sidewalls of the through-hole and surfaces of the first and second metal bases adjacent to and outside the through-hole and then electroplating a second metal on the first metal.

37. The method of claim 31, including forming the connection joints after forming the electrical interconnect.

38. The method of claim 31, including removing the attachment joint after forming the encapsulant base.

39. The method of claim 31, including forming an insulative material in the through-hole after forming the electrical interconnect in the through-hole, wherein the electrical interconnect contacts all sidewall portions of the through-hole without plugging the through-hole, and the insulative material contacts the electrical interconnect and fills all remaining space in the through-hole.

40. The method of claim 31, wherein the module is devoid of wire bonds, TAB leads and solder joints.

41. A method of making a semiconductor module, comprising:

providing a first semiconductor chip assembly that includes a first semiconductor chip and a first carrier, wherein the first chip includes a first conductive pad, and the first carrier includes a first metal base and a first conductive trace;

providing a second semiconductor chip assembly that includes a second semiconductor chip and a second carrier, wherein the second chip includes a second conductive pad, and the second carrier includes a second metal base and a second conductive trace;

mechanically attaching the first and second assemblies, thereby defining a chamber between the first and second assemblies;

filling an encapsulant base into the chamber;

forming a through-hole that extends through the first and second metal bases and the encapsulant base and exposes the first and second traces and is located outside the peripheries of the first and second chips;

forming an electrical interconnect in the through-hole that contacts the first and second traces; and

forming first and second connection joints, wherein the first connection joint contacts and electrically connects the first trace and the first pad, and the second connection joint contacts and electrically connects the second trace and the second pad.

42. The method of claim 41, wherein mechanically attaching the assemblies includes bending the first metal base near opposing lateral ends of the first metal base to form a pair of legs in the first metal base, and forming a pair of attachment joints that mechanically attach the legs to the second metal base.

43. The method of claim 42, wherein forming the attachment joints includes welding the legs to the second metal base.

44. The method of claim 42, including removing the legs and the attachment joints after filling the encapsulant base.

45. The method of claim 41, wherein filling the encapsulant base includes contacting the encapsulant base to the first and second chips, the first and second metal bases and the first and second traces in the chamber.

46. The method of claim 41, wherein filling the encapsulant base includes transfer molding the encapsulant base.

47. The method of claim 41, wherein forming the through-hole includes mechanically drilling the through-hole through the first and second metal bases, the first and second traces and the encapsulant base.

48. The method of claim 41, wherein forming the electrical interconnect includes electrolessly plating a metal on sidewalls of the through-hole.

49. The method of claim 41, including forming the connection joints after forming the electrical interconnect.

50. The method of claim 41, wherein the module is devoid of wire bonds, TAB leads and solder joints.

51. A semiconductor module, comprising:

a first semiconductor chip assembly that includes a first semiconductor chip, a first conductive trace and a first connection joint, wherein the first chip includes a first conductive pad, the first trace extends within and outside a periphery of the first chip, and the first connection joint contacts and electrically connects the first trace and the first pad;

a second semiconductor chip assembly that includes a second semiconductor chip, a second conductive trace and a second connection joint, wherein the second chip includes a second conductive pad, the second trace extends within and outside a periphery of the second chip, and the second connection joint contacts and electrically connects the second trace and the second pad;

an encapsulant base disposed between and in contact with the first and second chips and the first and second traces; and

an electrical interconnect disposed in a through-hole that extends through the encapsulant base and is located outside the peripheries of the first and second chips, wherein the electrical interconnect contacts the first and second traces in the through-hole, thereby electrically connecting the first and second traces.

52. The module of claim 51, wherein the first and second chips are vertically aligned with one another.

53. The module of claim 51, wherein the first pad faces away from the second chip, and the second pad faces away from the first chip.

54. The module of claim 51, wherein the first trace is a planar metal lead that overlaps the first pad, and the second trace is planar metal lead that overlaps the second pad.

55. The module of claim 51, wherein the encapsulant base is a molded insulator.

56. The module of claim 51, wherein the encapsulant base is plastic.

57. The module of claim 51, wherein the electrical interconnect contacts the first and second traces at first and second sidewall portions of the through-hole that are vertically spaced from one another and span 360 degrees around the through-hole.

58. The module of claim 51, wherein the electrical interconnect includes a metal that is electrolessly plated on sidewalls of the through-hole.

59. The module of claim 51, wherein the module is a dual in-line memory module.

60. The module of claim 51, wherein the module is devoid of wire bonds, TAB leads and solder joints.

61. A semiconductor module, comprising:

a first semiconductor chip assembly that includes a first semiconductor chip, a first conductive trace and a first connection joint, wherein the first chip includes a first top surface, a first bottom surface and first outer edges between the first top and bottom surfaces, the first top surface includes a first conductive pad, the first trace extends within and outside a periphery of the first chip, and the first connection joint contacts and electrically connects the first trace and the first pad;

a second semiconductor chip assembly that includes a second semiconductor chip, a second conductive trace and a second connection joint, wherein the second chip includes a second top surface, a second bottom surface and second outer edges between the second top and bottom surfaces, the second top surface includes a second conductive pad, the second trace extends within and outside a periphery of the second chip, and the second connection joint contacts and electrically connects the second trace and the second pad;

a transfer molded encapsulant base disposed between and in contact with the first and second chips and the first and second traces, wherein the encapsulant base contacts the first and second bottom surfaces and the first and second outer edges; and

an electrical interconnect disposed in a through-hole, wherein the through-hole extends through the first and second traces and the encapsulant base and is located outside the peripheries of the first and second chips, and the electrical interconnect covers vertical sidewalls of the through-hole and contacts the first and second traces at the sidewalls such that an electrically conductive path between the first and second pads consists of the first and second connection joints, the first and second traces and the plated metal interconnect.

62. The module of claim 61, wherein the first and second chips are vertically aligned with one another.

63. The module of claim 61, wherein the first pad faces away from the second chip, and the second pad faces away from the first chip.

64. The module of claim 61, wherein the first trace is a planar plated metal lead that overlaps the first pad, and the second trace is planar plated metal lead that overlaps the second pad.

65. The module of claim 61, wherein the encapsulant base is essentially coplanar with the first and second traces.

66. The module of claim 61, wherein the encapsulant base does not contact the first top surface and does not contact the second top surface.

67. The module of claim 61, wherein the encapsulant base is plastic.

68. The module of claim 61, wherein the electrical interconnect contacts the first trace at a first portion of the sidewalls that spans 360 degrees around the through-hole, contacts the second trace at a second portion of the sidewalls that spans 360 degrees around the through-hole, and contacts the encapsulant base at a third portion of the sidewalls that spans 360 degrees around the through-hole and is sandwiched between the first and second portions.

69. The module of claim 61, wherein the module is a dual in-line memory module.

70. The module of claim 61, wherein the module is devoid of wire bonds, TAB leads and solder joints.