Programmable logic array with vertical transistors

• US 6,486,703 B2
• Filed: 01/08/2001
• Issued: 11/26/2002
• Est. Priority Date: 08/04/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/756,099
• Publication Number:
  US 20010002109A1
• Time in Patent Office: 687 Days
• Field of Search: 326/37-41
• US Class Current: 326/41
• CPC Class Codes: H01L 27/11803 using field effect technology

Abstract

A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

Claims

1. A programmable logic array, comprising:

an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the conductive lines is a gate extending in one of the trenches adjacent the body region of at least one pillar, the gate only extending along one side of the at least one pillar;

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.

2. The array of claim 1, wherein a single conductive line is formed in each trench.

3. The array of claim 1, wherein at least two conductive lines are formed in each trench.

4. The array of claim 1, wherein a number of the conductive lines are formed in contact with the body region of pillars in their row.

5. The programmable logic array according to claim 1, wherein a first of the conductive lines contacts the body region of at least one of the pillars.

6. A programmable logic array, comprising:

an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars;

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and

wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed.

7. The programmable logic array according to claim 6, the second conductive line is an input line into the first logic plane.

8. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.

9. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars include pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.

10. The programmable logic array according to claim 9, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.

11. The programmable logic array according to claim 6, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.

12. A programmable logic array, comprising:

an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars;

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and

wherein a first of the conductive lines contacts the body region of at least one of the pillars, and the first conductive line is maintained at a constant voltage.

13. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.

14. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.

15. The programmable logic array according to claim 14, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.

16. The programmable logic array according to claim 12, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.

17. A programmable logic array, comprising:

an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars, a first of the conductive lines forming a gate of one of the pillars, a second of the conductive lines contacting the body region, the body region being pulsed in synchronization with the gate; and

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.

18. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.

19. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.

20. The programmable logic array according to claim 19, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.

21. The programmable logic array according to claim 17, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.

22. The programmable logic array according to claim 17, wherein the first source/drain regions of pillars in the first logic plane are coupled together.

23. A programmable logic array, comprising:

a substrate of a semiconductor material;

an array of monocrystalline semiconductor pillars formed on the substrate, each pillar extending in a first direction from the substrate and including a first source/drain region, a body region, and a second source/drain region that are aligned in the first direction, the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;

a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the number of conductive lines is a gate in one of the trenches adjacent the body region of at least one of the pillars, the gate extending along only one side of the pillar facing the one trench; and

an electrical connection beneath the pillars of the first logic plane electrically connecting the first source/drain region of each of the pillars of the first logic plane together.

24. The programmable logic array according to claim 23, wherein the electrical interconnection is a layer formed on the substrate beneath the pillars.

25. The programmable logic array according to claim 24, wherein the electrical interconnection layer is an N+ region.

26. The programmable logic array according to claim 25, wherein N+ interconnection layer is integral with the first source/drain regions of the pillars of the first logic plane.

27. The programmable logic array according to claim 23, wherein the first direction is generally perpendicular to the surface of the substrate.

28. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors; and

wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row.

29. The logic array according to claim 28, wherein the trenches include a third trench on a side of the second row of transistors opposite the second trench, the third trench includes third conductive line defining a third gate which is connected to the at least one transistor of the second row.

30. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;

wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and

wherein the first and second conductive lines receive the same input signal such that the at least one transistor operates as a single transistor.

31. The logic array according to claim 30, wherein the second trench includes a third conductive line that is connected to at least one transistor of a second row of the transistors.

32. The logic array according to claim 31, wherein a third trench is on a side of the second row of transistors opposite the second trench, and the third trench includes a fourth conductive line connected to at least one transistor of the second row of transistors.

33. The logic array according to claim 32, wherein the third and fourth conductive lines are connected to the same transistor.

34. The logic array according to claim 33, wherein the first, second, third, and fourth conductive lines all extend in a same direction.

35. The logic array according to claim 34, wherein the at least one transistor of the first row and the at least one transistor of the second row are positioned in different columns in the array.

36. The logic array according to claim 32, wherein the fourth conductive line is connected to all transistors in the second row.

37. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row; and

wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor.

38. The logic array according to claim 37, wherein the second conductive line is connected to all of the transistors in the first row.

39. The logic array of claim 37, wherein the first gate is connected to only one side of the at least one of the transistors in the first row.

40. The logic array of claim 39, wherein the second gate is connected to only a second side of the at least one of the transistors in the first row.

41. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;

wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row; and

wherein the second conductive line through the second and third gates controls formation of a conducting region in the at least one transistors of both the first and second rows of transistors.

42. The logic array of claim 41, wherein the substrate includes a conductive layer on which the first source/drain regions are formed.

43. The logic array of claim 41, wherein the substrate includes a conductive layer, and wherein the first source/drain regions of the first logic plane are integrally formed with the conductive layer.

44. The logic array of claim 42, wherein the substrate includes a conductive layer, and wherein the first source/drain regions of the first logic plane are doped the same as the conductive layer.

45. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;

wherein the trenches include a third trench on a side of the second row of transistors opposite the second trench, the third trench includes third conductive line defining a third gate which is connected to the at least one transistor of the second row; and

wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor of the first row operates as two transistors with one channel region on each side of the at least one transistor of the first row.

46. The logic array according to claim 45, wherein the second conductive line applies the second input signal to the third gate and the third conductive line applies a third input signal to the third gate such that the at least one transistor of the second row operates as two transistors with one channel region on each side of the at least one transistor of the second row.

47. A method of forming an IC logic array, comprising:

forming a first source\drain layer on a substrate;

forming a body layer on the first source\drain layer;

forming a second source\drain layer on the body layer;

removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a first plurality of trenches extending in a first direction;

filling the first trenches with an insulator;

removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a second plurality of trenches extending in a second direction;

removing the insulator from the first trenches so as to form an array of pillars each of which include the second source\drain layer, the body layer and at least a portion of the first source\drain layer;

selectively forming a first conductive line in the first trench connected to at least one of the body layer to form a gate; and

selectively forming a second conductive line in the second trench connected to the at least one of the body layer to form a body layer contact, wherein the second conductive line is formed separate from the first conductive line.

48. The method according to claim 47, wherein forming the conductive line includes forming an insulative layer on the sides of the pillars in the one of the first and second trenches, selectively removing the insulative layer from the sides of the select pillars, forming a conductive line in the one of the first and second trenches which contacts the select pillars with the insulative layer removed and is spaced from the non-select pillars on which the insulative layer remains such that gates are formed on the select pillars but not on the non-select pillars.

49. The method according to claim 47, wherein forming the conductive lines includes only removing a portion of the first source\drain layer such that the pillars are electrically connected by the first source\drain layer.

50. The method according to claim 47, wherein forming the conductive lines includes forming body contacts in trenches connected to select pillars.

51. A programmable logic array, comprising:

an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars;

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;

wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed; and

wherein the first source/drain regions of pillars in the first logic plane are coupled together.

52. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars are formed on a substrate, and the substrate is a bulk semiconductor.

53. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.

54. The programmable logic array according to claim 53, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.

55. The programmable logic array according to claim 51, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.

56. An IC programmable logic array comprising:

substrate;

a conductive layer on the substrate;

an array of monocrystalline semiconductor pillars on the conductive layer, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

a number of conductive lines disposed in trenches that separate adjacent pillars;

the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;

wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed.

57. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are coupled together.

58. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are formed on the conductive layer.

59. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are integrally formed with the conductive layer.

60. The IC programmable logic array of claim 56, wherein the first source/drain regions of pillars in the first logic plane are doped the same as the conductive layer.

61. The IC programmable logic array according to claim 56, wherein the substrate is a bulk semiconductor.

62. The IC programmable logic array according to claim 56, wherein the array of monocrystalline semiconductor pillars includes pillars arranged in rows and columns, the first conductive line is positioned in a first trench on one side of a row of pillars, and the second conductive line is positioned in a second trench on a second side of the row of pillars.

63. The IC programmable logic array according to claim 62, wherein the first trench and the second trench are arranged on opposite sides of the pillars in the row.

64. The programmable logic array according to claim 56, wherein the array of monocrystalline semiconductor pillars are arranged in rows and columns and separated by orthogonal trenches.

65. An IC logic array, comprising:

a substrate;

a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;

a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;

a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;

a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;

wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and

wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor operates as two transistors with one channel region on each side of the at least one vertical transistor.

66. The logic array of claim 65, wherein the first gate is connected to only a first side of the transistor.

67. The logic array of claim 65, wherein the first gate is connected to only a first side of the transistor, wherein the second gate is only to a second side of the transistor, and wherein the first side is separated from the second side.