Programmable logic array with vertical transistors
First Claim
Patent Images
1. A programmable logic array, comprising:
- an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the conductive lines is a gate extending in one of the trenches adjacent the body region of at least one pillar, the gate only extending along one side of the at least one pillar;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.
7 Assignments
0 Petitions
Accused Products
Abstract
A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
-
Citations
67 Claims
-
1. A programmable logic array, comprising:
-
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the conductive lines is a gate extending in one of the trenches adjacent the body region of at least one pillar, the gate only extending along one side of the at least one pillar;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A programmable logic array, comprising:
-
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed. - View Dependent Claims (7, 8, 9, 10, 11)
-
-
12. A programmable logic array, comprising:
-
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function; and
wherein a first of the conductive lines contacts the body region of at least one of the pillars, and the first conductive line is maintained at a constant voltage. - View Dependent Claims (13, 14, 15, 16)
-
-
17. A programmable logic array, comprising:
-
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars, a first of the conductive lines forming a gate of one of the pillars, a second of the conductive lines contacting the body region, the body region being pulsed in synchronization with the gate; and
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function. - View Dependent Claims (18, 19, 20, 21, 22)
-
-
23. A programmable logic array, comprising:
-
a substrate of a semiconductor material;
an array of monocrystalline semiconductor pillars formed on the substrate, each pillar extending in a first direction from the substrate and including a first source/drain region, a body region, and a second source/drain region that are aligned in the first direction, the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the number of conductive lines is a gate in one of the trenches adjacent the body region of at least one of the pillars, the gate extending along only one side of the pillar facing the one trench; and
an electrical connection beneath the pillars of the first logic plane electrically connecting the first source/drain region of each of the pillars of the first logic plane together. - View Dependent Claims (24, 25, 26, 27)
-
-
28. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors; and
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row. - View Dependent Claims (29)
-
-
30. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and
wherein the first and second conductive lines receive the same input signal such that the at least one transistor operates as a single transistor. - View Dependent Claims (31, 32, 33, 34, 35, 36)
-
-
37. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row; and
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor. - View Dependent Claims (38, 39, 40)
-
-
41. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor of the first row; and
wherein the second conductive line through the second and third gates controls formation of a conducting region in the at least one transistors of both the first and second rows of transistors. - View Dependent Claims (42, 43, 44)
-
-
45. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row and a third gate connected to at least one of the transistors in a second row of the first plurality of transistors;
wherein the trenches include a third trench on a side of the second row of transistors opposite the second trench, the third trench includes third conductive line defining a third gate which is connected to the at least one transistor of the second row; and
wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor of the first row operates as two transistors with one channel region on each side of the at least one transistor of the first row. - View Dependent Claims (46)
-
-
47. A method of forming an IC logic array, comprising:
-
forming a first source\drain layer on a substrate;
forming a body layer on the first source\drain layer;
forming a second source\drain layer on the body layer;
removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a first plurality of trenches extending in a first direction;
filling the first trenches with an insulator;
removing a plurality of portions of the second source\drain layer, the body layer, and the first source\drain layer so as to form a second plurality of trenches extending in a second direction;
removing the insulator from the first trenches so as to form an array of pillars each of which include the second source\drain layer, the body layer and at least a portion of the first source\drain layer;
selectively forming a first conductive line in the first trench connected to at least one of the body layer to form a gate; and
selectively forming a second conductive line in the second trench connected to the at least one of the body layer to form a body layer contact, wherein the second conductive line is formed separate from the first conductive line. - View Dependent Claims (48, 49, 50)
-
-
51. A programmable logic array, comprising:
-
an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed; and
wherein the first source/drain regions of pillars in the first logic plane are coupled together. - View Dependent Claims (52, 53, 54, 55)
-
-
56. An IC programmable logic array comprising:
-
substrate;
a conductive layer on the substrate;
an array of monocrystalline semiconductor pillars on the conductive layer, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;
a number of conductive lines disposed in trenches that separate adjacent pillars;
the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function;
wherein a first of the conductive lines contacts the body region of at least one of the pillars, a second of the conductive lines is a gate connected to the body region of the at least one of the pillars, and the first conductive line and the second conductive line are synchronously pulsed. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64)
-
-
65. An IC logic array, comprising:
-
a substrate;
a first plurality of vertical transistors formed on the substrate, the first plurality of transistors forming a first logic plane, each of the first plurality of transistors including a first source/drain region, a body region, and a second source/drain region, the transistors being separated from each other by trenches;
a second plurality of transistors formed on the substrate, the second plurality of transistors forming a second logic plane in electrical communication with the first logic plane;
a first conductive line positioned in a first of the trenches adjacent one side of a first row of the first plurality of transistors, wherein the first conductive line forms a first gate connected to at least one of the transistors in the first row;
a second conductive line positioned in a second of the trenches adjacent a second side of the first row of the plurality of transistors, wherein the second conductive line defines a second gate connected to the at least one of the transistors in the first row;
wherein the first and second conductive lines each selectively receive input signals to control operation of the at least one transistor; and
wherein the first conductive line applies a first input signal to the first gate and the second conductive lines applies a second input signal to the second gate such that the at least one transistor operates as two transistors with one channel region on each side of the at least one vertical transistor. - View Dependent Claims (66, 67)
-
Specification