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Programmable logic array with vertical transistors

  • US 6,486,703 B2
  • Filed: 01/08/2001
  • Issued: 11/26/2002
  • Est. Priority Date: 08/04/1998
  • Status: Expired due to Term
First Claim
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1. A programmable logic array, comprising:

  • an array of monocrystalline semiconductor pillars, each pillar including a first source/drain region, a body region, and a second source/drain region that are vertically aligned in the pillar;

    a number of conductive lines disposed in trenches that separate adjacent pillars, wherein one of the conductive lines is a gate extending in one of the trenches adjacent the body region of at least one pillar, the gate only extending along one side of the at least one pillar;

    the pillars being selectively interconnected to form first and second logic planes that implement a desired logical function.

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