Apparatus and method for updating images stored in non-volatile memory

• US 6,486,883 B1
• Filed: 06/18/1999
• Issued: 11/26/2002
• Est. Priority Date: 06/18/1999
• Status: Expired due to Term

• Current Assignee: Kinglite Holdings Inc.
• Original Assignee: Phoenix Technologies Limited (Pharaoh Acquisition LLC)
• Inventors: Mathur, Sameer
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/336,356
• Time in Patent Office: 1,257 Days
• Field of Search: 345/568, 345/564-567, 345/520, 345/501, 345/733, 711/200, 711/202, 711/203, 711/206, 711/208, 711/209, 703/27
• US Class Current: 345/568
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A method and apparatus is described in which a firmware causes display of a graphical screen with various images that are stored in a non-volatile memory wherein the images may be selectively updated. A memory is configured into a plurality of memory segments wherein each memory segment has a predetermined address thereby allowing the segment to be selectively addressed. A circuit is able to configure a display template having a plurality of display sections on a display wherein data stored in the mentioned memory segments is displayed on a predetermined display section.

Claims

1. An apparatus comprising:

a non-volatile memory including a plurality of non-volatile memory segments, each of said plurality of non-volatile memory segments having a predetermined address to allow selective access thereto;

a first circuit for receiving an updating image to update an old image;

a second circuit, coupled to said first circuit, for translating a logical address included in said updating image into a physical address corresponding to at least one of said predetermined addresses of said plurality of non-volatile memory segments;

a third circuit for selecting one of the plurality of non-volatile memory segments based on said physical address;

a fourth circuit, coupled to the non-volatile memory, for updating said one of the plurality of non-volatile memory segments with said updating image; and

a fifth circuit adapted to configure a display template having a plurality of display sections on a display wherein said updating image stored in said one of the plurality of non-volatile memory segments is displayed on a predetermined display section.

2. The apparatus as in claim 1, further comprising an interface port adapted to receive said updating image through an internet.

3. The apparatus as in claim 1, wherein said second circuit includes an Address Translation Unit (ATU) to translate said logical address included in said updating image into a corresponding one of said predetermined addresses of said plurality of non-volatile memory segments.

4. The apparatus of as in claim 3 wherein said fourth circuit is adapted to store said updating image in said one of the plurality of non-volatile memory segments as a bitmap of said display.

5. A method comprising:

receiving an updating image to update an old image;

translating a logical address included in said updating image into a physical address;

selecting one of a plurality of non-volatile memory segments based on said physical address;

updating said one of the plurality of non-volatile memory segments with said updating image; and

displaying said updating image stored in said one of the plurality of non-volatile memory segments on a predetermined display section on a display.

6. The method as in claim 5, further comprising:

receiving said updating image from an internet.

7. The method as in claim 5, wherein updating said one of the plurality of non-volatile memory segment comprises storing said updating image in said one of the plurality of non-volatile memory segment as a bitmap of said display.

8. The method of claim 5, wherein said predetermined display section is linked to said one of the plurality of non-volatile memory segments.

9. The method of claim 5 wherein displaying said updating image comprises displaying, during a boot period, said updating image stored in said one of the plurality of non-volatile memory segments on the predetermined display section on the display.

10. A processor readable medium which, when executed by a processor, causes said processor to perform a method comprising:

receiving an updating image to update an old image;

translating a logical address included in said updating image into a physical address;

selecting one of a plurality of non-volatile memory segments based on said physical address;

updating said one of the plurality of non-volatile memory segments with said updating image; and

displaying said updating image stored in said one of the plurality of non-volatile memory segments on a predetermined display section on a display.

11. The processor readable medium as in claim 10, further comprising:

receiving said updating image from an internet.

12. The processor readable medium as in claim 10, wherein updating said one of the plurality of non-volatile memory segments comprises storing said updating image in said one of the plurality of non-volatile memory segments as a bitmap of said display.

13. A computer data signal comprising:

a code segment to receive updating image to update an old image;

a translate code segment to translate a logical address included in said updating image into a physical address;

a selection code segment to select one of a plurality of non-volatile memory segments based on said physical address;

an update code segment to update said one of the plurality of non-volatile memory segments with said updating image; and

a display code segment to display said updating image stored in said one of the plurality of non-volatile memory segments on a predetermined display section on a display.

14. The computer data signal as in claim 13, further comprising a receive code segment to receive said updating image from an internet.

15. The computer data signal as in claim 13, wherein said update code segment to update said one of the plurality of non-volatile memory segments comprises a store code segment to store said updating image in said one of the plurality of non-volatile memory segments as a bitmap of said display.

16. A computer system comprising:

a processor;

a non-volatile memory coupled to said processor, said non-volatile memory including a plurality of non-volatile memory segments, each of said non-volatile memory segments having a predetermined address to allow a selective access thereto;

an interface port coupled to said non-volatile memory, said interface port adapted to receive data;

a first circuit for translating a logical address included in a received data into a physical address corresponding to at least one of said predetermined addresses of said plurality of non-volatile memory segments;

a second circuit for selecting one of the plurality of non-volatile memory segments based on said physical address;

a third circuit to update data stored in said one of the plurality of non-volatile memory segments with said received data; and

a fourth circuit to configure a display template having a plurality of display sections on a display wherein data stored in said one of the plurality of non-volatile memory segments is displayed on a predetermined display section.

17. The computer system as in claim 16, wherein said interface port is adapted to receive data through an internet.

18. The computer system as in claim 16, wherein said first circuit includes an Address Translation Unit (ATU) to translate said logical address included in said received data into a corresponding one of said predetermined addresses of said plurality of non-volatile memory segments.

19. The computer system of claim 16 wherein said predetermined display section is linked to said one of the plurality of non-volatile memory segments.

20. The computer system of claim 16 wherein said fourth circuit comprises a fourth circuit to configure the display template having the plurality of display sections on the display wherein data stored in said one of the plurality of non-volatile memory segments is displayed on the predetermined display section during a boot period.