Semiconductor device simulating apparatus and semiconductor test program debugging apparatus using it

• US 6,487,700 B1
• Filed: 03/08/2000
• Issued: 11/26/2002
• Est. Priority Date: 03/15/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Fukushima, Kiyoshi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US09/520,428
• Time in Patent Office: 993 Days
• Field of Search: 714/22-23, 714/25, 714/718, 714/724, 714/734-736, 714/740, 714/743, 714/726, 714/732, 714/735, 714/738, 714/741, 327/198, 716/4-6
• US Class Current: 716/106
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

Abstract

Herein disclosed is a semiconductor device simulation apparatus which is set the various parameters to be used for measuring a current value and a voltage value that varies depending on the internal resistance of a DUT, and simulates a current value or a voltage value that varies depending on an internal resistance of a DUT in accordance with various parameters and a prescribed test signal when receiving the test signal. Also disclosed is a semiconductor test program debugging apparatus using such a semiconductor device simulating apparatus.

Claims

1. A semiconductor device simulating apparatus for simulation operation as if an actual DUT were present, comprising:

parameter setting unit for setting various parameters to be used for measuring a current value or a voltage value that varies depending on an internal resistance of a DUT;

input unit for inputting a test signal for as would be applicable to said actual DUT; and

simulating unit for simulating and outputting a current value or a voltage value that varies depending on an internal resistance of said actual DUT in accordance with said parameters and said test signal as if said actual DUT were present, without requiring said actual DUT to be present.

2. The semiconductor device simulating apparatus according to claim 1, wherein said parameters include a first parameter indicating a voltage value and a resistance value in a case where a signal pin representative of a signal pin of said actual DUT is in a high level state, a second parameter indicating a voltage value and a resistance value in a case where said signal pin is in a low level state, a third parameter indicating a resistance value in a case where said signal pin is in a high impedance state, a fourth parameter indicating which of the high level state, low level state, and the high impedance state said signal pin is in, and a fifth parameter indicating a current value or a voltage value to be applied to said signal pin in a current source voltage measurement or a voltage source current measurement.

3. The semiconductor device simulating apparatus according to claim 2, wherein said simulating unit simulates a voltage value that would appear at said signal pin in the current source voltage measurement based on said first to fifth parameters and said test signal.

4. The semiconductor device simulating apparatus according to claim 2, wherein said simulating unit simulates a current value that would appear at said signal pin in the voltage source current measurement based on said first to fifth parameters and said test signal.

5. The semiconductor device simulating apparatus according to claim 1, wherein said parameters set by said parameter setting unit include a sixth parameter indicating a resistance value corresponding to a power source pin of said actual DUT and a seventh parameter indicating a current value or a voltage value as would be applicable to said power source pin.

6. The semiconductor device simulating apparatus according to claim 5, wherein said simulating unit simulates a voltage value that would appear at said power source pin in a current source voltage measurement based on said sixth and seventh parameters and said test signal.

7. The semiconductor device simulating apparatus according to claim 5, wherein said simulating unit simulates a current value that would appear at said power source pin in a voltage source current measurement based on said sixth and seventh parameters and said test signal.

8. The semiconductor device simulating apparatus according to claim 1, wherein said parameters include a first parameter indicating a voltage value and a resistance value in a case where a signal pin representative of a signal pin of said actual DUT is in a high level state, a second parameter indicating a voltage value and a resistance value in a case where said signal pin is in a low level state, a third parameter indicating a resistance value in a case where said signal pin is in a high impedance state, and a fourth parameter indicating which of the high level state, low level state, and the high impedance state said signal pin is in, and wherein said test signal indicates a condition relating to a load that is to be connected to said signal pin.

9. A semiconductor test program debugging apparatus comprising:

tester emulating unit for setting various parameters to be used for measuring a current value or a voltage value that varies depending on an internal resistance of an actual DUT, and for emulating an operation of a semiconductor test apparatus by generating a simulatory test signal as would be applicable to an actual DUT based on a semiconductor test program;

device simulating unit receiving said parameters and said test signal, for simulating and outputting a current value or a voltage value that varies depending on an internal resistance of said actual DUT in accordance with said parameters and said test signal; and

debugging unit for debugging said semiconductor test program based on an output of said device simulating unit.