System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology

• US 6,487,701 B1
• Filed: 11/13/2000
• Issued: 11/26/2002
• Est. Priority Date: 11/13/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Keller, Emory D., Hayes, Jerry D., Iadanza, Joseph A., Ventrone, Sebastian T., Dean, Alvar A.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US09/711,744
• Time in Patent Office: 743 Days
• Field of Search: 716/1-21, 363/74, 365/226, 365/227, 365/228, 365/229, 365/201
• US Class Current: 716/136
• CPC Class Codes: G01R 31/2891 related to sensing or controlling of force, position, temperature G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05
• CPC Class Codes: G01R 31/3163 Functional testing

Abstract

A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, V_T, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC'"'"'s circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.

Claims

1. A method for reducing AC test failures during performance testing of an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, said method comprising:

analyzing each of said plurality of circuits against a plurality of performance verification test cases;

identifying failed circuits that do not pass said plurality of performance verification test cases;

calculating voltage threshold values for said failed circuits;

performing a static timing analysis on said plurality of circuits, substituting said calculated voltage threshold values for said bulk well voltages;

programming said integrated circuit wafer to operate at said calculated voltage threshold values that pass said static timing analysis; and

,

reanalyzing said plurality of circuits having programmed said calculated voltage threshold values against said plurality of performance verification tests.

2. The method of claim 1 wherein said analyzing each of said plurality of circuits further comprises:

generating a gate level netlist of said plurality of circuits; and

,

simulating said netlist on a functional delay simulator against a library of said performance verification test cases and technology circuit delay timing rules.

3. The method of claim 1 wherein said bulk well voltages are initially preconditioned using nominal bias values.

4. The method of claim 3 wherein said nominal bias values are chosen such that there is a trade off between timing performance and power dissipation due to leakage currents.

5. The method of claim 2 wherein performing said static timing analysis further comprises analyzing said gate level netlist.

6. The method of claim 2 wherein calculating said voltage threshold values further comprises basing said voltage threshold values on said delay timing rules and said static timing analysis.

7. The method of claim 6 further comprising incrementing voltage rails that identify said bulk well voltages required for each of said plurality of gates.

8. The method of claim 7 further comprising characterizing said plurality of gates based on said incremental voltage rails required by said delay timing rules.

9. The method of claim 2 wherein said library of performance verification test cases is predetermined by investigating critical circuit paths from a dynamic timing analysis and a static timing analysis.

10. The method of claim 1 wherein each of said performance verification test cases is performed for a separately controlled section of said plurality of circuits.

11. The method of claim 1 further comprising generating a plurality of nodes or circuit toggles as a function of each of said performance verification test cases.

12. The method of claim 11 further comprising analyzing circuit activity by logging said plurality of circuit toggles during each of said performance verification test cases.

13. The method of claim 12 further comprising generating a correlation table of said circuit activity against said performance verification test cases.

14. A method of adjusting voltage thresholds for reducing AC test failures during integrated circuit wafer testing, said wafer having a plurality of gates, circuits, and bulk well voltages, said method comprising:

generating a gate level netlist for said integrated circuit wafer;

performing static timing analyses on said gate level netlist;

simulating said gate level netlist against performance verification test cases;

generating integrated circuit simulation traces for said plurality of circuits;

calculating an expected frequency versus process profile;

assigning pass/fail timing criteria for each of said performance verification test cases;

exercising said performance verification test cases against said plurality of circuits;

correlating circuit failures of said performance verification test cases to said plurality of circuits;

analyzing and isolating said circuit failures in said integrated circuit wafer based on said pass/fail timing criteria;

calculating a list of voltage threshold shifts corresponding to said bulk well voltages;

verifying set-up and hold margins of said plurality of circuits using said list of voltage threshold shifts;

obtaining voltage threshold corrections; and

,

applying said voltage threshold corrections to all sites on said integrated circuit wafer.

15. The method of claim 14 wherein said bulk well voltages are initially preconditioned using nominal bias values.

16. The method of claim 15 wherein said nominal bias values are chosen such that there is a trade off between timing performance and power dissipation due to leakage currents.

17. The method of claim 14 wherein said static timing analyses are performed on a static analyzer.

18. The method of claim 14 wherein performing said static timing analyses on said gate level netlist further comprises incorporating technology circuit delay timing rules.

19. The method of claim 18 wherein said timing rules support timing as a function of said bulk well voltage biasing.

20. The method of claim 18 further comprising incrementing voltage rails that identify said bulk well voltages required for each of said gates.

21. The method of claim 14 further comprising generating said performance verification test cases by investigating critical circuit paths from said static timing analyses and dynamic timing analyses.

22. The method of claim 14 wherein each of said performance verification test cases is performed for a separately controlled section of said plurality of circuits.

23. The method of claim 14 further comprising generating a plurality of nodes or circuit toggles as a function of each of said performance verification test cases.

24. The method of claim 23 further comprising analyzing circuit activity by logging said plurality of circuit toggles during each of said performance verification test cases.

25. The method of claim 24 further comprising generating a correlation table of said circuit activity against said performance verification test cases.

26. The method of claim 14 wherein correlating said circuit failures further comprises generating a correlation database and an initial timing slack report for each failed test to find worst case slack circuits.

27. The method of claim 26 wherein verifying said set-up and hold margins further comprises updating said initial timing slack report when no fail is detected, and ceasing operation when said fail is detected.

28. The method of claim 27 wherein verifying said set-up and hold margins further comprises reverifying hardware for functional performance.

29. The method of claim 14 further comprising applying said method to a single site in said wafer and adjusting said threshold voltages until all of said threshold voltages are corrected.

30. The method of claim 29 further comprising applying said method to all other sites on said wafer.

31. A processor based system including a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, said method steps comprising:

analyzing each of said plurality of circuits against a plurality of performance verification test cases;

identifying failed circuits that do not pass said plurality of performance verification test cases;

calculating voltage threshold values for said failed circuits;

performing a static timing analysis on said plurality of circuits, substituting said calculated voltage threshold values for said bulk well voltages;

programming said integrated circuit wafer to operate at said calculated voltage threshold values that pass said static timing analysis; and

,

reanalyzing said plurality of circuits having programmed said calculated voltage threshold values against said plurality of performance verification tests.

32. The system of claim 31 wherein said method step of analyzing each of said plurality of circuits further comprises:

generating a gate level netlist of said plurality of circuits; and

,

simulating said netlist on a functional delay simulator against a library of said performance verification test cases and technology circuit delay timing rules.

33. The system of claim 31 wherein said bulk well voltages are initially preconditioned using nominal bias values.

34. The system of claim 32 wherein said method step of performing said static timing analysis further comprises analyzing said gate level netlist.

35. The system of claim 32 wherein said method step of calculating said voltage threshold values further comprises basing said voltage threshold values on said delay timing rules and said static timing analysis.

36. The system of claim 32 wherein said library of performance verification test cases is predetermined by investigating critical circuit paths from a dynamic timing analysis and a static timing analysis.

37. The system of claim 31 wherein each of said performance verification test cases is performed for a separately controlled section of said plurality of circuits.

38. A computer program product comprising:

a computer usable medium having computer readable program code means embodied therein for causing AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the computer readable program code means in said computer program product comprising;

computer readable program code means for causing a computer to effect analyzing each of said plurality of circuits against a plurality of performance verification test cases;

computer readable program code means for causing a computer to effect identifying failed circuits that do not pass said plurality of performance verification test cases;

computer readable program code means for causing a computer to effect calculating voltage threshold values for said failed circuits;

computer readable program code means for causing a computer to effect performing a static timing analysis on said plurality of circuits, substituting said calculated voltage threshold values for said bulk well voltages;

computer readable program code means for causing a computer to effect programming said integrated circuit wafer to operate at said calculated voltage threshold values that pass said static timing analysis; and

,

computer readable program code means for causing a computer to effect reanalyzing said plurality of circuits having programmed said calculated voltage threshold values against said plurality of performance verification tests.

39. A computer program product comprising:

a computer usable medium having computer readable program code means embodied therein for causing AC performance tuning by threshold voltage shifting on an integrated circuit wafer having a plurality of gates, circuits, and bulk well voltages, the computer readable program code means in said computer program product comprising;

computer readable program code means for causing a computer to effect generating a gate level netlist for said integrated circuit wafer;

computer readable program code means for causing a computer to effect performing static timing analyses on said gate level netlist;

computer readable program code means for causing a computer to effect simulating said gate level netlist against performance verification test cases;

computer readable program code means for causing a computer to effect generating integrated circuit simulation traces for said plurality of circuits;

computer readable program code means for causing a computer to effect calculating an expected frequency versus process profile;

computer readable program code means for causing a computer to effect assigning pass/fail timing criteria for each of said performance verification test cases;

computer readable program code means for causing a computer to effect exercising said performance verification test cases against said plurality of circuits;

computer readable program code means for causing a computer to effect correlating circuit failures of said performance verification test cases to said plurality of circuits;

computer readable program code means for causing a computer to effect analyzing and isolating said circuit failures in said integrated circuit wafer based on said pass/fail timing criteria;

computer readable program code means for causing a computer to effect calculating a list of voltage threshold shifts corresponding to said bulk well voltages;

computer readable program code means for causing a computer to effect verifying set-up and hold margins of said plurality of circuits using said list of voltage threshold shifts;

computer readable program code means for causing a computer to effect obtaining voltage threshold corrections; and

,

computer readable program code means for causing a computer to effect applying said voltage threshold corrections to all sites on said integrated circuit wafer.