Timing optimization and timing closure for integrated circuit models

• US 6,487,705 B1
• Filed: 09/05/2001
• Issued: 11/26/2002
• Est. Priority Date: 09/05/2001
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Incorporated (NEC Corporation)
• Original Assignee: NEC Electronics Incorporated (NEC Corporation)
• Inventors: Kovacs-Birkas, Attila, Roethig, Wolfgang
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US09/946,240
• Time in Patent Office: 447 Days
• Field of Search: 716/1-2, 716/4-7, 716/9-18, 703/19
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method correlates a timing target for electronic design automation (EDA) design tools by comparing slack distributions. A method of designing an integrated circuit can include designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization and placement of cells with embedded timing analysis and optimization. The method can also include designing an integrated circuit by routing with embedded timing analysis and optimization; performing reference timing analysis; performing reference timing analysis and embedded timing analysis using a parasitic estimation model. The method can also include comparing at least two slack distributions resulting from timing analyses. The method can include calculating and comparing autocorrelation functions of slack distributions. The method can include calculating interrcorrelation functions of slack distributions. An embodiment teaches an integrated circuit designed by the method taught. Another embodiment teaches a computer program product according to the method taught.

Claims

1. A method of designing an integrated circuit, comprising:

designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization;

designing an integrated circuit by placement of cells with embedded timing analysis and optimization;

designing an integrated circuit by routing of interconnect between cells with embedded timing analysis and optimization;

performing reference timing analysis on the result of the integrated circuit design;

performing reference timing analysis and embedded timing analysis using a parasitic estimation model, a timing model for arc, timing constraints and exceptions from designer; and

comparing a first slack distribution resulting from a first timing analyses to a second slack distribution resulting from a second timing analyses.

2. The method of designing an integrated circuit as recited in claim 1, further comprising:

based on the comparing step, identifying a cause of a mismatch between a first slack distribution and a second slack distribution.

3. The method of designing an integrated circuit as recited in claim 2, further comprising:

comparing a total number of paths reported in slack distribution.

4. The method of designing an integrated circuit as recited in claim 3, further comprising:

calculating and comparing autocorrelation functions of slack distributions.

5. The method of designing an integrated circuit as recited in claim 2, further comprising:

calculating an interrcorrelation function of a slack distribution.

6. The method of designing an integrated circuit as recited in claim 2, further comprising:

calculating an autocorrelation function of a slack distribution;

calculating an interrcorrelation function a plurality of slack distributions; and

comparing the autocorrelation function with the interrecorrelation function.

7. The method of designing an integrated circuit as recited in claim 2, further comprising:

correcting a cause of a mismatch between slack distributions.

8. The method of designing an integrated circuit as recited in claim 7, further comprising:

calibrating a parasitic estimation model after a cause of a mismatch has been corrected.

9. The method of designing an integrated circuit as recited in claim 1, further comprising:

identifying a cause of a mismatch between a first slack distribution and a second slack distribution; and

correcting a cause of a mismatch between a first slack distribution and a second distribution, wherein correcting a cause of a mismatch between a first slack distribution and a slack distribution further comprises;

modifying a timing constraint; and

selecting a parasitic estimation model.

10. The method of designing an integrated circuit as recited in claim 1, further comprising:

based on the comparing step, calibrating a parasitic estimation model.

11. The method of designing an integrated circuit as recited in claim 1, further comprising:

performing RTL synthesis but not performing layout;

checking timing constraint compatibility for all embedded timing analyses performed on the result of RTL synthesis; and

modifying timing constraints.

12. The method of designing an integrated circuit as recited in claim 1, further comprising:

performing a design step after performing RTL synthesis;

selecting a parasitic estimation model after performing one subsequent design step;

repeating a design steps if a selected parasitic model is not suitable; and

changing a structural hierarchy if a selected parasitic model is not suitable.

13. An integrated circuit designed by a method, the method comprising:

designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization;

designing an integrated circuit by placement of cells with embedded timing analysis and optimization;

designing an integrated circuit by routing of interconnect between cells with embedded timing analysis and optimization;

performing reference timing analysis on the result of the integrated circuit design;

performing reference timing analysis and embedded timing analysis using a parasitic estimation model, a timing model for arc, timing constraints and exceptions from designer; and

comparing a first slack distribution resulting from a first timing analyses to a second slack distribution resulting from a second timing analyses.

14. The integrated circuit as recited in claim 13, further comprising:

based on the comparing step, identifying a cause of a mismatch between a first slack distribution and a second slack distribution.

15. The integrated circuit as recited in claim 14, further comprising:

comparing a total number of paths reported in a slack distribution.

16. The integrated circuit as recited in claim 15, further comprising:

calculating and comparing a first autocorrelation function of a first slack distribution to a second autocorrelation function of a second slack distribution.

17. The integrated circuit as recited in claim 14, further comprising:

calculating an interrcorrelation function of a slack distribution.

18. The integrated circuit as recited in claim 14, further comprising:

calculating an autocorrelation function of a slack distribution;

calculating an interrcorrelation function of a plurality of slack distributions; and

comparing the autocorrelation function with the interrecorrelation function.

19. The integrated circuit as recited in claim 14, further comprising:

correcting a cause of a mismatch between slack distributions.

20. The integrated circuit as recited in claim 19, further comprising:

calibrating a parasitic estimation model after a cause of a mismatch has been corrected.

21. The integrated circuit as recited in claim 13, further comprising:

identifying a cause of a mismatch between a first slack distribution and a second slack distribution; and

correcting a cause of a mismatch between a first slack distribution and a second distribution, wherein correcting a cause of a mismatch between a first slack distribution and a slack distribution further comprises;

modifying a timing constraint; and

selecting a parasitic estimation model.

22. The integrated circuit as recited in claim 13, further comprising:

calibrating a parasitic estimation model.

23. A computer program product, the computer program product encoded in computer readable media, the computer program product comprising:

a set of instructions, executable on a computer system, configured to;

design an integrated circuit by RTL synthesis with embedded timing analysis and optimization;

design an integrated circuit by placement of cells with embedded timing analysis and optimization;

design an integrated circuit by routing of interconnect between cells with embedded timing analysis and optimization;

perform reference timing analysis on the result of the integrated circuit design;

perform reference timing analysis and embedded timing analysis using a parasitic estimation model, a timing model for arc, timing constraints and exceptions from designer; and

compare a first slack distribution resulting from a first timing analyses to a second slack distribution resulting from a second timing analyses.

24. The computer program product as recited in claim 23, further comprising:

a set of instructions configured to;

based on the comparing step, identify a cause of a mismatch between a first slack distribution and a second slack distribution.

25. The computer program product as recited in claim 24, further comprising:

a set of instructions configured to;

compare a total number of paths reported in a first slack distribution with a total number of paths reported in a second slack distribution.

26. The computer program product as recited in claim 25, further comprising:

a set of instructions configured to;

calculate a first autocorrelation function of a first clack distribution;

calculate a second autocorrelation function of a first slack distribution; and

compare the first autocorrelation function to the second autocorrelation function.

27. The computer program product as recited in claim 24, further comprising:

a set of instructions, configured to;

calculate an interrecorelation function of a slack distribution.

28. The computer program product as recited in claim 24, further comprising:

a set of instructions configured to;

calculate an autocorrelation function of a slack distribution;

calculate an interrcorrelation function a plurality of slack distributions; and

compare the autocorrelation function with the interrecorrelation function.

29. The computer program product as recited in claim 24, further comprising:

a set of instructions configured to;

correct a cause of a mismatch between a first slack distribution and a second slack distribution.

30. The computer program product as recited in claim 29, further comprising:

a set of instructions configured to;

calibrate a parasitic estimation model after a cause of a mismatch has been corrected.

31. The computer program product as recited in claim 23, further comprising:

a set of instructions configured to;

identify a cause of a mismatch between a first slack distribution and a second slack distribution; and

correct a cause of a mismatch between a first slack distribution and a second distribution, wherein correcting a cause of a mismatch between a first slack distribution and a slack distribution further comprises;

modifying a timing constraint; and

selecting a parasitic estimation model.

32. The computer program product as recited in claim 23, further comprising:

a set of instructions configured to;

calibrate a parasitic estimation model.

33. The computer program product as recited in claim 23, further comprising:

a set of instructions configured to;

perform RTL synthesis but not performing layout;

check timing constraint compatibility for all embedded timing analyses performed on the result of RTL synthesis; and

modify timing constraints.

34. The computer program product as recited in claim 23, further comprising:

a set of instructions configured to;

perform a design step after performing RTL synthesis;

select a parasitic estimation model after performing one subsequent design step;

repeat a design steps if a selected parasitic model is not suitable; and

change a structural hierarchy if a selected parasitic model is not suitable.