Contract methodology for concurrent hierarchical design

• US 6,487,706 B1
• Filed: 08/30/2000
• Issued: 11/26/2002
• Est. Priority Date: 08/30/2000
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Barkley, Keith G., Camporese, Peter J., Eng, Kwok Fai
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US09/651,464
• Time in Patent Office: 818 Days
• Field of Search: 700/97, 716/4, 716/10, 716/2, 716/9, 716/8, 716/1, 716/21
• US Class Current: 716/112
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it. The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools.

Claims

1. A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, comprising the steps of:

defining a size for the chip of a hierarchical design,

removing blocked areas, including clock and power grid areas, leaving the wiring channels available for interconnecting the individual elements of the VLSI chip, from said available area,

allocating a percentage of wiring levels for global and local wiring as parallel iterations for the global and local wiring; and

as the parallel iterations for the global and local wiring progress, modifying the percentage to be allocated for global and local wiring, and

during the parallel iterative process increasing the number of wires for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire; and

defining a vertical slice of wiring resources used for the space above a macro entity, and

checking the macro entity with the context of the VLSI chip physical design above it; and

implementating a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools and wherein said blockage modeling tool keeps any adjacent wire at a spacing value greater than a minimum spacing away from a wire when the width of a wire is greater than a rule defined width.

2. The method according to claim 1 wherein said blockage modeling tool adds an artificial blockage to guide the routing tools to wire a design without shorts or DRC violations when there is a wide wire and its metal overlap past a via and its width is above a certain width and spaced less than a predetermined value from an adjacent wire on the same metal layer.