Method of manufacturing a taped semiconductor device

• US 6,489,183 B1
• Filed: 07/20/2000
• Issued: 12/03/2002
• Est. Priority Date: 07/17/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M.
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/620,991
• Time in Patent Office: 866 Days
• Field of Search: 438/110, 438/111, 438/112, 438/113, 438/106, 438/108, 438/118, 438/119, 438/125, 438/126, 438/127, 438/613, 438/461, 438/615, 257/668, 257/723, 257/738, 257/773, 257/782, 257/783, 298/41, 298/49, 298/55, 298/56, 298/27
• US Class Current: 438/112
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: Y10T 29/49121 Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49172 by molding of insulating material

Abstract

Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low temperature curing adhesive material may be used to reduce the effects of differential thermal expansion between the tape and surface of the wafer. In another embodiment of the invention, anisotropically conductive adhesive material is used to connect bond pads on a wafer to leads printed on a tape.

Claims

1. A method of making semiconductor devices, said method comprising the steps of:

providing a semiconductor product having integrated circuits;

providing a tape having an adhesive layer, a dielectric layer, and electrically conductive leads;

adhering said tape to said semiconductor product; and

electrically connecting said integrated circuits to said electrically conductive leads,

said step of adhering the tape comprising curing the adhesive layer to ninety percent of its maximum strength within twenty-four to thirty-six hours at room temperature.

2. The method of claim 1, wherein the temperature of said tape does not exceed one hundred fifty degrees Fahrenheit during said adhering step.

3. The method of claim 2, wherein said step of electrically connecting said integrated circuits to said leads includes the step of connecting bond wires to bond pads on said semiconductor product.

4. The method of claim 3, further comprising the step of locating ball grid arrays on said electrically conductive leads.

5. The method of claim 4, further comprising the step of encapsulating said bond wires in resin.

6. The method of claim 5, further comprising the step of dicing said semiconductor product to separate said integrated circuits into individual semiconductor chips.

7. A method of making taped products, said method comprising the steps of:

providing a sheet having electrically conductive leads and an epoxy adhesive layer;

aligning said sheet with respect to integrated circuits; and

curing said adhesive layer to ninety percent of its maximum strength within twenty-four to thirty-six hours at room temperature.

8. The method of claim 7, further comprising the step of connecting wires to said integrated circuits and said electrically conductive leads.

9. The method of claim 8, wherein the temperature of said adhesive layer does not exceed one hundred degrees Fahrenheit during said curing step.

10. The method of claim 9, further comprising the step of connecting ball grid arrays to said leads.

11. The method of claim 10, further comprising the step of flowing resin through a mask to glob top encapsulate said wires.

12. The method of claim 11, further comprising the step of separating said integrated circuits from each other to produce integrated circuit devices.