Base current reversal SRAM memory cell and method

• US 6,489,192 B2
• Filed: 01/08/2001
• Issued: 12/03/2002
• Est. Priority Date: 03/16/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Brock, II, Paul E
• Application Number:
  US09/757,683
• Publication Number:
  US 20010010376A1
• Time in Patent Office: 694 Days
• Field of Search: 438/202-208
• US Class Current: 438/202
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Claims

1. A method of forming a memory cell comprising:

forming a series of epitaxial layers on a substrate;

etching trenches through the series of epitaxial layers to form a series of bars;

forming an oxide under the bars to electrically isolate the bars from the substrate;

forming a NPN bipolar transistor on top of the oxide; and

forming a PMOS FET having a source, the PMOS FET formed on top of the NPN bipolar transistor and within one of the trenches, the NPN bipolar transistor formed in the source of the PMOS FET.

2. The method of claim 1 wherein forming the PMOS FET comprises forming a vertical PMOS FET.

3. A method of forming an array of memory cells, comprising:

forming a plurality of epitaxial layers on a substrate;

etching trenches through the plurality of epitaxial layers to form columns of epitaxial layers;

forming an oxide under the columns of epitaxial layers;

forming storage devices in a lower layer of the epitaxial layers of the columns; and

forming access elements within the trenches and on a surface of the columns.

4. The method of claim 3 wherein forming a storage device comprises forming a NPN bipolar transistor.

5. The method of claim 3 wherein forming an access element comprises forming a vertical PMOS FET having source and drain regions formed from two of the epitaxial layers of the columns.

6. The method of claim 3 wherein forming the storage devices comprises forming a NPN bipolar transistor in a source of a PMOS FET comprising the access element.

7. The method of claim 3 wherein forming the oxide under the columns of epitaxial layers comprises forming the oxide layer in a portion of the lower layer of the epitaxial layers.

8. A method of forming a memory cell comprising:

forming a stack of epitaxial layers on a substrate, the stack having a sidewall surface;

forming an oxide under the stack of epitaxial layers;

forming a storage device in a first layer of the epitaxial layers of the stack; and

forming an access element on the sidewall surface of the stack.

9. The method of claim 8 wherein forming a storage device in the first layer of the epitaxial layers of the stack comprises forming a NPN bipolar transistor.

10. The method of claim 8 wherein forming an access element comprises forming a vertical FET device having source and drain regions formed from two of the epitaxial layers of the stack.

11. The method of claim 8 where in forming a storage device comprises forming a NPN bipolar transistor in a source of a PMOS FET comprising the access element.

12. The method of claim 8 wherein forming an oxide under the columns of epitaxial layers comprises forming the oxide layer in a portion of the first layer of the epitaxial layers.