Save MOS device

• US 6,489,204 B1
• Filed: 08/20/2001
• Issued: 12/03/2002
• Est. Priority Date: 08/20/2001
• Status: Expired due to Fees

• Current Assignee: Episil Technologies Incorporated
• Original Assignee: Episil Technologies Incorporated
• Inventors: Tsui, Bing-Yue
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): VOCKRODT, JEFF B
• Application Number:
  US09/932,727
• Time in Patent Office: 470 Days
• Field of Search: 438/206, 438/212, 438/242, 438/270, 438/271, 438/272, 438/243, 257/302, 257/329
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.

Claims

1. A process for manufacturing a vertical power MOSFET, comprising:

(a) providing a silicon wafer having an N+ bottom layer, an N type middle layer, and a P body top layer having an upper surface;

(b) on said P body top layer, forming a layer of pad oxide and depositing thereon a layer of silicon nitride;

(c) patterning the silicon nitride and pad oxide layers to form a mask that defines a trench, having a floor and sidewalls, and then etching said trench to a depth sufficient to extend into said N type middle layer;

(d) forming a first layer of silicon oxide on said floor and sidewalls;

(e) overfilling the trench with polysilicon and then etching back the polysilicon until said polysilicon under-fills the trench;

(f) removing from the sidewalls all exposed silicon oxide;

(g) forming a second layer of silicon oxide on the polysilicon exposed sidewalls, whereby all polysilicon in the trench is now encapsulated in a layer of silicon oxide;

(h) through ion implantation by an ion beam, forming an N+ source area, part of which overlaps and abuts said polysilicon encapsulating oxide layer then removing said layer of silicon nitride;

(i) depositing a conformal layer of a dielectric material and then selectively removing all dielectric material on horizontal surfaces whereby insulating spacers on the walls of the trench are formed;

(j) implanting acceptor ions to form a P+ region that abuts said N+ source area; and

(k) forming a silicide contact to the polysilicon and a single silide contact to both the N+ source area and to said P+ region that is abutted thereto.

2. The process described in claim 1 wherein said ion beam is directed at the silicon wafer at an angle, relative to the vertical, of between about 30 and 60 degrees while the wafer rotates relative to the beam.

3. The process described in claim 1 wherein the ion beam is arsenic ions having an energy between about 30 and 80 kilovolts, said ions being deposited to achieve a concentration between about 5×

10¹⁹ and 5×

10²⁰ ions per cc.

4. The process described in claim 1 wherein step (e) is replaced as follows:

(e) overfilling the trench with polysilicon, then planarizing the wafer until there is no polysilicon outside the trench, and then removing an amount of polysilicon from the trench by means of reactive ion etching or chemical etching.

5. The process described in claim 1 wherein the dielectric material is selected from the group consisting of silicon oxide and silicon nitride.

6. The process described in claim 1 wherein the insulating spacers extend upwards from the polysilicon as far the upper surface of the wafer.

7. The process described in claim 1 wherein the insulating spacers extend upwards from the polysilicon as far as between about 0.1 and 0.3 microns below the upper surface of the wafer.

8. The process described in claim 1 wherein said silicide contact is selected from the group consisting of titanium silicide, cobalt silicide, and nickel silicide.

9. The process described in claim 1 further comprising adding a punch through implantation after step (i) and before step (j)thereby enabling source to source spacing to be reduced.

10. A process for manufacturing a vertical power MOSFET, comprising:

(a) providing a silicon wafer having an N+ bottom layer, an N type middle layer, and a P body top layer having an upper surface;

(b) on said P body top layer, forming a layer of pad oxide and depositing thereon a layer of silicon nitride;

(c) patterning the silicon nitride and pad oxide layers to form a mask that defines a trench, having a floor and sidewalls, and then etching said trench to a depth sufficient to extend into said N type middle layer;

(d) forming a layer of silicon oxide on said floor and sidewalls;

(e) overfilling the trench with polysilicon and then etching back the polysilicon until said polysilicon under-fills the trench;

(f) removing from the sidewalls all exposed silicon oxide;

(g) through diffusion from a diffusion source, forming an N+ source area, that extends outwards from the sidewalls above the polysilicon into the P body layer;

(h) removing from the sidewalls any byproducts of the diffusion performed in step (g) and then removing the layer of silicon nitride;

(i) depositing a conformal layer of a dielectric material and then selectively removing all dielectric material on horizontal surfaces whereby insulating spacers on the walls of the trench are formed;

(j) implanting acceptor ions to form P+ region that abuts said N+ source area; and

(k) forming a silicide contact to the polysilicon and a single silicide contact to both the N+ source area and to said P+ region that is abutted thereto.

11. The process described in claim 10 wherein said diffusion source is phosphorus oxychloride gas.

12. The process described in claim 10 wherein said diffusion source is a layer of glass selected from the group consisting of phosphosilicate glass and arsenosilicate glass.

13. The process described in claim 10 wherein step (e) is replaced as follows:

(e) overfilling the trench with polysilicon, then planarizing the wafer until there is no polysilicon outside the trench, and then removing an amount of polysilicon from the trench by means of reactive ion etching or chemical etching.

14. The process described in claim 10 wherein the dielectric material is selected from the group consisting of silicon oxide and silicon nitride.

15. The process described in claim 10 wherein the insulating spacers extend upwards from the polysilicon as far the upper surface of the wafer.

16. The process described in claim 10 wherein the insulating spacers extend upwards from the polysilicon as far as between about 0.1 and 0.3 microns below the upper surface of the wafer.

17. The process described in claim 10 wherein said silicide contact is selected from the group consisting of titanium silicide, cobalt silicide, and nickel silicide.

18. The process described in claim 10 further comprising adding a punch through implantation after step (i) and before step (j) thereby enabling source to source spacing to be reduced.