Pixel circuit with selectable capacitor load for multi-mode X-ray imaging

• US 6,489,619 B2
• Filed: 04/27/2001
• Issued: 12/03/2002
• Est. Priority Date: 04/27/2001
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Street, Robert A.
• Primary Examiner(s): Hannaher, Constantine
• Assistant Examiner(s): Moran, Timothy J.
• Application Number:
  US09/844,382
• Publication Number:
  US 20020158206A1
• Time in Patent Office: 585 Days
• Field of Search: 250/370.01, 250/370.08, 250/370.09, 250/370.14, 250/371, 257/443, 257/444, 257/448
• US Class Current: 250/370.09
• CPC Class Codes: G01N 23/04 and forming images of the material

Abstract

Each pixel of an image sensor array includes a capacitive load that is selectively coupled to or decoupled from the usual sensor capacitance to facilitate dual mode operation. During a first operating mode (e.g., a high-power operating mode such as radiography), a global enable signal is asserted to turn on a mode control transistor of each pixel that couples the selectable capacitive load to the sensor, thereby increasing the total capacitance of the pixels. During a second operating mode (e.g., a low-power operating mode such as fluoroscopy), the global enable signal is de-asserted, thereby decoupling the optional capacitive load from the sensor to minimize pixel capacitance. An amorphous silicon sensor includes an additional metal plate located below the lower sensor plate to provide the optional capacitive load. The additional metal plate is formed from the same metal layer that is used to fabricate the gate lines of the array.

Claims

1. An imaging apparatus including a sensor array having a plurality of pixel circuits and control circuitry for detecting electrical signals from the pixel circuits representative of radiation incident on the pixel circuits, wherein each pixel circuit comprises:

a sensor having a first terminal connected to a first voltage source;

a first transistor connected between a second terminal of the sensor and a data line; and

a capacitor circuit including a first capacitor connected in series with a second transistor between the second terminal of the sensor and a second voltage source.

2. The imaging apparatus according to claim 1, wherein the first capacitor is connected between the second transistor and the second voltage source.

3. The imaging apparatus according to claim 1, wherein the second transistor is connected between the first capacitor and the second voltage source.

4. The imaging apparatus according to claim 1, wherein the sensor comprises:

a first conductive layer connected to a first terminal of the first transistor;

a charge sensing layer formed on the first conductive layer; and

a second conductive layer formed over the charge sensing layer.

5. The imaging apparatus according to claim 4, wherein the charge sensing layer comprises at least one of amorphous silicon, selenium, lead iodide, benzimidazole perylene, and tetraphenyldiamine.

6. The imaging apparatus according to claim 4, wherein the first capacitor comprises a third conductive layer formed below the first conductive layer and connected to a first terminal of the second transistor.

7. The imaging apparatus according to claim 6, wherein a gate of the first transistor is formed by a first metal line;

wherein a gate of the second transistor is formed by a second metal line; and

wherein the third conductive layer, the first metal line, and the second metal line are etched from a single metal layer.

8. The imaging apparatus according to claim 1, further comprising a second capacitor connected in parallel with the capacitor circuit between the second terminal of the sensor and the second voltage source.

9. The imaging apparatus according to claim 8, wherein the sensor comprises:

a first conductive layer connected to a first terminal of the first transistor;

a charge sensing layer formed on the first conductive layer; and

a second conductive layer formed over the charge sensing layer,

wherein the first capacitor comprises a third conductive layer formed below a first region of the first conductive layer and connected to a first terminal of the second transistor, and

wherein the second capacitor comprises a fourth conductive layer formed below a second region of the first conductive layer and connected to the second voltage source.

10. The imaging apparatus according to claim 9,

wherein a gate of the first transistor is formed by a first metal line,

wherein a gate of the second transistor is formed by a second metal line, and

wherein the third conductive layer, the fourth conductive layer, the first metal line, and the second metal line are etched from a single metal layer.

11. The imaging apparatus according to claim 1, further comprising a second capacitor circuit connected in parallel with the capacitor circuit between the second terminal of the sensor and the second voltage source, the second capacitor circuit including a second capacitor connected in series with a third transistor.

12. The imaging apparatus according to claim 1, further comprising a phosphor converter mounted between the sensor and a source of high-energy radiation beams.

13. The imaging apparatus according to claim 1, wherein the first and second transistors comprise thin-film transistors.

14. A pixel circuit comprising:

a sensor;

a first transistor having a first terminal connected to the sensor and a second terminal connected to a data line; and

a capacitor circuit connected between the first terminal of the first transistor and a voltage source, the capacitor circuit including a capacitor connected in series with a second transistor.

15. The pixel circuit according to claim 14, wherein the second transistor is connected between the capacitor and the first terminal of the first transistor.

16. The pixel circuit according to claim 14, wherein the capacitor is connected between the second transistor and the first terminal of the first transistor.

17. The pixel circuit according to claim 14, further comprising a second capacitor connected in parallel with the capacitor circuit between the first terminal of the first transistor and the voltage source.

18. The pixel circuit according to claim 14, further comprising a second capacitor circuit connected in parallel with the capacitor circuit between the first terminal of the first transistor and the voltage source, the second capacitor circuit including a second capacitor connected in series with a third transistor.

19. The pixel circuit according to claim 14, wherein the sensor comprises:

a first conductive layer connected to the first terminal of the first transistor;

a charge sensing layer formed on the first conductive layer; and

a second conductive layer formed over the charge sensing layer.

20. A method for selectively operating a sensor array in one of a radiographic mode or and fluoroscopic mode, the sensor array having a plurality of pixel circuits, each pixel circuit including a sensor and a capacitor circuit including a capacitor connected in series with a mode control transistor between the sensor and ground, the method comprises:

during the radiographic mode, setting a total capacitance of each pixel circuit to a relatively high capacitance level by turning on the mode control transistor to couple the sensor of each pixel circuit to the capacitor of said each pixel circuit; and

during the fluoroscopic mode, setting the total capacitance of each pixel circuit to a relatively low capacitance level by turning off the mode control transistor, thereby decoupling the capacitor from the sensor of each pixel circuit.