MOS transistor that inhibits punchthrough

• US 6,489,651 B1
• Filed: 06/16/2000
• Issued: 12/03/2002
• Est. Priority Date: 12/30/1997
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated, ANAM Semiconductor Incorporated (DB HiTek Co., Ltd.)
• Inventors: Kim, Sang Yong
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US09/595,851
• Time in Patent Office: 900 Days
• Field of Search: 438/197, 438/424, 438/429, 438/207, 438/218, 438/221, 438/225, 438/294, 438/296, 438/297, 438/299, 257/330, 257/362, 257/497, 257/344, 257/336, 257/408, 257/510, 257/900
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled with polysilicon; a gate conductor formed over the trench region; and source/drain regions formed within the well region laterally aligned to the gate conductor. A suitable method to form the MOS transistor includes the acts of: forming a well region in a semiconductor substrate; forming a trench region in the well region; forming an isolator in a corner of the trench region; filling the trench region with polysilicon; forming a gate conductor formed over the trench region; and forming source/drain regions within the well region on opposite sides of the gate conductor.

Claims

1. A MOS transistor having a semiconductor substrate, comprising:

a transistor area defined by a first isolation area formed in the semiconductor substrate, the semiconductor substrate having an upper surface;

a gate oxide layer formed over the transistor area;

a gate conductor formed over the gate oxide layer, wherein the gate conductor defines a channel region;

a source and a drain; and

a second isolator formed in the substrate between the source and the drain and below the upper surface of the semiconductor substrate, the gate oxide layer and the gate conductor;

wherein the second isolator does not extend to the upper surface of the semiconductor substrate.

2. The MOS transistor of claim 1 wherein the second isolator is formed in the substrate so that its upper side is closer to the upper surface than a depth of the source/drain region.

3. The MOS transistor of claim 1 wherein when a voltage is applied across the source and the drain, a depletion region is formed at a bottom surface of each of the source and the drain and extends into the semiconductor substrate, the second isolator inhibiting the depletion region from expanding beyond a topmost surface of the second isolator.

4. A MOS transistor comprising:

a semiconductor substrate having an upper surface;

a well region formed in the semiconductor substrate, wherein a trench is defined in the well region, the trench having a top surface located at the upper surface of the semiconductor substrate;

an isolator formed on a corner of the trench region, wherein the trench is filled to the top surface with polysilicon;

a gate conductor formed over the top surface of the trench; and

a source and a drain formed within the well region laterally aligned to the gate conductor.

5. The MOS transistor of claim 4 wherein the isolator is formed in the substrate so that its upper side is closer to an upper surface of the semiconductor substrate than a depth of the source and the drain.

6. The MOS transistor of claim 4 wherein when a voltage is applied across the source and the drain, a depletion region is formed at a bottom surface of each of the source and the drain and extends into the semiconductor substrate, the isolator inhibiting the depletion region from expanding beyond a topmost surface of the isolator.

7. The MOS transistor of claim 4 wherein the source and the drain region have a depth in the semiconductor substrate that extends below a topmost surface of said isolator.

8. The MOS transistor of claim 4, wherein the isolator does not extend to the top surface of the trench.

9. A MOS transistor having a semiconductor substrate comprising:

a transistor area formed in a trench region of the semiconductor substrate, the semiconductor substrate having an upper surface, the trench having a bottom surface, a top surface, and corners at the bottom surface;

a gate conductor above the trench region and the upper surface of the semiconductor substrate, wherein the gate conductor defines a channel region;

source and drain regions, the trench region located in the channel region and between the source and drain regions; and

isolating regions located in the corners of the trench region, wherein the trench region is filled with polysilicon, and the isolating regions do not extend to the top surface of the trench.

10. The MOS transistor of claim 9 wherein when a voltage is applied across the source region and the drain region, a depletion region is formed at a bottom surface of each of the source and drain regions and extends into the semiconductor substrate, the isolating regions inhibiting the depletion region from expanding beyond a topmost surface of the isolating regions.

11. The MOS transistor of claim 9 wherein the source and the drain have a depth in the semiconductor substrate that extends below a topmost surface of said isolator.

12. A MOS transistor comprising:

a semiconductor substrate having an upper surface;

a trench in the semiconductor substrate between a source and a drain, said trench having a top surface, a bottom surface, a corner at the bottom surface, a sidewall, and a depth below the top surface, the top surface of the trench located at the upper surface of the semiconductor substrate;

an isolator formed on each bottom corner of the trench, each isolator having a height from the bottom surface of the trench, the height of each isolator less than the depth of the trench, wherein the trench is filled with polysilicon;

a gate conductor formed above the top surface of the trench and the upper surface of the substrate.

13. The MOS transistor of claim 12 wherein a portion of the isolator is located below at least a portion of a depletion region formed at a bottom surface of each of the source and the drain when a voltage is applied across the source and the drain, the isolator inhibiting the depletion region from expanding beyond a topmost surface of the isolator.

14. A MOS transistor having a semiconductor substrate comprising:

a transistor area formed in a trench region of the semiconductor substrate, the semiconductor substrate having an upper surface, the trench having a bottom surface, a top surface, and corners at the bottom surface, the top surface of the trench located at the upper surface of the semiconductor substrate;

a gate conductor above the trench region and the upper surface of the semiconductor substrate, wherein the gate conductor defines a channel region;

source and drain regions, the trench region located in the channel region and between the source and drain regions; and

isolating regions located in the corners of the trench region, wherein the trench region is filled to the top surface with polysilicon and the isolating regions do not extend to the top surface of the trench.

15. The MOS transistor of claim 14 wherein the isolating regions are formed in the substrate so that an upper side of the isolating regions is closer to the upper surface of the substrate than a depth of the source and drain regions.

16. The MOS transistor of claim 14 wherein the source and the drain have a depth in the semiconductor substrate that extends below a topmost surface of said isolator.