Trench DMOS device having a high breakdown resistance

• US 6,489,652 B1
• Filed: 11/01/1996
• Issued: 12/03/2002
• Est. Priority Date: 11/11/1995
• Status: Expired due to Fees

• Current Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Jeon, Chang-Ki, Jang, Young-Soo
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/742,754
• Time in Patent Office: 2,223 Days
• Field of Search: 257/328-342, 438/270, 438/272, 438/274
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.

Claims

1. A trench semiconductor device, comprising:

a trench formed in a semiconductor substrate, said trench having sidewalls, a bottom, and bottom corners where the sidewalls and bottom merge;

a gate polysilicon layer substantially filled into said trench; and

a gate oxide layer formed between said gate polysilicon layer and said sidewalls, said bottom and said bottom corners of said trench, said gate oxide layer having a first portion on said sidewalls and a second portion on said bottom, said second portion being thicker than said first portion and comprising a central region bounded by boundary regions, wherein said central region is raised step-wise at angles of approximately ninety degrees from said boundary regions and has a substantially flattened top surface, and wherein the transitions between steps of said central and said boundary regions are substantially planar.

2. The trench semiconductor device as in claim 1, wherein said first portion contacts said second portion only in said boundary region without contacting said central region.

3. The trench device of claim 1, wherein said boundary region has a substantially flat surface.

4. A trench semiconductor device, comprising:

a semiconductor substrate having a trench formed therein, said trench having sidewalls, a bottom, and bottom corners where the sidewall and bottom merge;

a gate oxide layer disposed on said sidewalls, said bottom and said bottom corners of said trench, said gate oxide layer having a sidewall portion on said sidewalls of said trench, a bottom portion on said bottom of said trench, the bottom portion being thicker than the sidewall portion, and a bottom corner portion on said bottom corners of said trench; and

a gate layer substantially filled into said trench with said gate oxide layer being between the gate layer and said semiconductor substrate, wherein said bottom portion of said gate oxide layer includes a central region bounded by boundary regions, said central region being thicker than said boundary region, raised step-wise at angles of approximately ninety degrees from said boundary regions, and having a substantially flat top surface and wherein the transitions between steps of said central and said boundary regions are substantially planar.

5. The trench device of claim 4, wherein said sidewall portion contacts said bottom portion only in said boundary region without contacting said central region.

6. The trench device of claim 4, wherein said boundary region has a substantially flat surface.

7. A trench semiconductor device, comprising:

a trench formed in a semiconductor substrate, the trench having sidewalls, a bottom and corners where the sidewalls and bottom merge;

a conductive gate material substantially filling the trench; and

a gate dielectric layer formed between the conductive gate material and both the trench bottom and the trench sidewalls, the gate dielectric material at the bottom of the trench being thicker than the gate dielectric material along the sidewalls and including a flat-topped protrusion centered and extending along the bottom of the trench in a direction substantially parallel to the sidewalls of the trench, the flat-topped protrusion having edges that are substantially planar from the top of the protrusion to the bottom and that are laterally spaced from the sidewalls of the trench and that are substantially perpendicular to the top of the protrusion.

8. The trench device of claim 7, wherein the gate dielectric layer between a sidewall of the trench and an edge of the protrusion has a substantially flat surface.