Area efficient bond pad placement

• US 6,489,688 B1
• Filed: 05/02/2001
• Issued: 12/03/2002
• Est. Priority Date: 05/02/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Zeevo, Inc. (Broadcom, Inc.)
• Inventors: Pandula, Louis, Baumann, Doug
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US09/847,948
• Time in Patent Office: 580 Days
• Field of Search: 257/666, 257/691, 257/778, 257/202, 257/203, 257/503, 257/773, 257/776, 257/786, 257/909, 438/108, 438/128, 438/129, 438/612, 438/666
• US Class Current: 257/786
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

Embodiments of the present invention provide flip-chip bond pad arrangements that lead to a smaller increase in die size than conventional approaches. This is accomplished by using the core side of a periphery I/O pad ring for placing some of the bond pads in order to meet the bond pad pitch requirements of flip chip technology. For example, alternating bond pads are moved inward to the core side of the I/O pads or drivers, to meet the bond pad pitch requirement between the bond pads that are moved to the core side as well the bond pads that remain outside of the core. Because the bond pads are moved inward instead of outward, the increase in the die size from the edge of the I/O pad ring is reduced. In an alternative embodiment, the bond pads are each bonded on top of an active circuitry of a corresponding I/O pad. In another alternative embodiment, the bond pads are disposed between I/O pads which are spaced from each other by a spacing in the direction of the periphery of the core to accommodate the bond pads.

Claims

1. An integrated circuit device comprising:

a plurality of I/O pads disposed and oriented along a periphery of a core; and

a plurality of bond pads for the I/O pads, each bond pad being bonded on top of an active circuitry of a corresponding I/O pad, the bond pads being spaced along the periphery of the core by a minimum bond pad pitch,

wherein each bond pad has a bond pad height which matches a height of the corresponding I/O pad to which the bond pad is bonded.

2. The device of claim 1 wherein the minimum bond pad pitch is 300 μ

m.

3. The device of claim 1 further comprising a plurality of power buses extending along the I/O pads parallel to the periphery of the core and to the I/O pads.

4. The device of claim 1 wherein the plurality of I/O pads are arranged into a plurality of rows of I/O pad rings around the periphery of the core.

5. The device of claim 4 further comprising a plurality of power buses extending along the I/O pad rings parallel to the periphery of the core and to the I/O pads.

6. The device of claim 4 further comprising a plurality of power buses extending across the I/O pad rings and across the core.

7. The device of claim 6 wherein the power buses provide power to both the core and the I/O pads.

8. An integrated circuit device comprising:

a plurality of I/O pads disposed and oriented along a periphery of a core;

a plurality of bond pads for the I/O pads, each bond pad being bonded on top of an active circuitry of a corresponding I/O pad, the bond pads being spaced along the periphery of the core by a minimum bond pad pitch; and

a plurality of power buses extending along the I/O pads parallel to the periphery of the core and to the I/O pads.

9. The device of claim 8 wherein the minimum bond pad pitch is 300 μ

m.

10. An integrated circuit device comprising:

a plurality of I/O pads disposed and oriented along a periphery of a core; and

a plurality of bond pads for the I/O pads, each bond pad being bonded on top of an active circuitry of a corresponding I/O pad, the bond pads being spaced along the periphery of the core by a minimum bond pad pitch,

wherein the plurality of I/O pads are arranged into a plurality of rows of I/O pad rings around the periphery of the core.

11. The device of claim 10 further comprising a plurality of power buses extending along the I/O pad rings parallel to the periphery of the core and to the I/O pads.

12. The device of claim 10 further comprising a plurality of power buses extending across the I/O pad rings and across the core.

13. The device of claim 12 wherein the power buses provide power to both the core and the I/O pads.

14. The device of claim 10 wherein the minimum bond pad pitch is 300 μ

m.

15. An integrated circuit device comprising:

a plurality of I/O pads disposed along and oriented transverse to a periphery of a core, the I/O pads being spaced from each other by spacings in a direction along the periphery of the core; and

a plurality of bond pads for the I/O pads, the bond pads being distributed along the periphery of the core and being disposed in the spacings between the I/O pads.

16. The device of claim 15 wherein the I/O pads and bond pads are alternately disposed along the periphery of the core.

17. The device of claim 15 wherein the bond pads are spaced from each other by a minimum bond pad pitch.

18. The device of claim 17 wherein the minimum bond pad pitch is 300 μ

m.

19. The device of claim 15 wherein the core has no I/O pads disposed therein.