Level shifter for ultra-deep submicron CMOS designs
First Claim
1. A level shifting circuit comprising:
- a circuit input that swings between a low supply and ground;
a circuit output that swings between a high supply and said ground;
an inverter with input connected to said circuit input and output forming inverted circuit input;
a first NMOS transistor with gate is connected to said circuit input and with source connected to said ground;
a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, and with drain connected to said first NMOS transistor drain;
a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and with drain connected to said circuit output;
a second PMOS transistor with gate connected to said first NMOS transistor drain, with source connected to said high supply, and with drain connected to said circuit output;
a transistion pulse circuit with output wherein said output is ground at steady state and wherein said output pulses to said low supply for a short duration when said circuit input changes state; and
a third NMOS transistor with gate connected to said output of said transition pulse circuit, with source connected to said circuit output, and with drain connected to said first NMOS transistor drain.
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Abstract
New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.
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Citations
13 Claims
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1. A level shifting circuit comprising:
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a circuit input that swings between a low supply and ground;
a circuit output that swings between a high supply and said ground;
an inverter with input connected to said circuit input and output forming inverted circuit input;
a first NMOS transistor with gate is connected to said circuit input and with source connected to said ground;
a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, and with drain connected to said first NMOS transistor drain;
a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and with drain connected to said circuit output;
a second PMOS transistor with gate connected to said first NMOS transistor drain, with source connected to said high supply, and with drain connected to said circuit output;
a transistion pulse circuit with output wherein said output is ground at steady state and wherein said output pulses to said low supply for a short duration when said circuit input changes state; and
a third NMOS transistor with gate connected to said output of said transition pulse circuit, with source connected to said circuit output, and with drain connected to said first NMOS transistor drain. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A level shifting circuit comprising:
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a circuit input that swings between a low supply and ground;
a circuit output that swings between a high supply and said ground;
an inverter with input connected to said circuit input and output forming inverted circuit input;
a first NMOS transistor with gate is connected to said circuit input and with source connected to said ground;
a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, and with drain connected to said first NMOS transistor drain;
a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and with drain connected to said circuit output;
a second PMOS transistor with gate connected to said first NMOS transistor drain, with source connected to said high supply, and with drain connected to said circuit output;
an exclusive NOR (XNOR) gate with first input connected to said circuit input, with said second input connected to said inverted circuit input, and with output that pulses to said low supply for a short duration when said circuit input changes state; and
a third NMOS transistor with gate connected to said exclusive NOR gate output, with source connected to said circuit output, and with drain connected to said circuit input. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification
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- Resources
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsChen, Chung-Hui, Wang, Wen-Tai
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Primary Examiner(s)Cunningham, Terry D.
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Assistant Examiner(s)NGUYEN, LONG T
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Application NumberUS10/156,626Publication NumberTime in Patent Office189 DaysField of Search327/333, 327/55, 327/57, 327/427, 327/434, 327/437, 326/63, 326/68, 326/80, 326/81US Class Current327/333CPC Class CodesH03K 3/012 Modifications of generator ...H03K 3/356113 using additional transistor...H03K 3/356182 with additional means for c...
