Crosstalk suppression in differential AC coupled multichannel IC amplifiers

• US 6,489,850 B2
• Filed: 03/16/2001
• Issued: 12/03/2002
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Orser, David John, Heineke, Randolph B., Olson, Scott Allen
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/810,133
• Publication Number:
  US 20020130722A1
• Time in Patent Office: 627 Days
• Field of Search: 330/295, 330/307, 330/124.R, 330/297, 257/723, 257/728, 257/499, 257/532
• US Class Current: 330/307
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multichannel parallel IC amplifier includes a plurality of amplifier circuits formed on an IC substrate. Each amplifier circuit is coupled to respective inputs via a pair of capacitors. The capacitors are configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels, leading to cancellation of crosstalk signals.

Claims

1. A multichannel IC amplifier, comprising a plurality of amplifier circuits formed on an IC substrate, each amplifier circuit defining a channel and each amplifier circuit coupled to respective inputs via a pair of capacitors, the capacitors being configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels.

2. The multichannel IC amplifier of claim 1, wherein each capacitor is configured in an L-shape.

3. The multichannel IC amplifier of claim 2, wherein the L-shaped capacitors for each channel are nested to form a rectangle.

4. The multichannel IC amplifier of claim 1, wherein the plurality of amplifier circuits consists of four amplifier circuits.

5. The multichannel IC amplifier of claim 1, wherein the amplifier circuits are differential amplifiers.

6. A method of suppressing crosstalk between adjacent channels in a multichannel IC amplifier, comprising coupling substantially equal crosstalk signals to each capacitor of a pair of capacitors for a given channel.

7. The method of claim 6, further comprising rejecting the coupled crosstalk signals at a differential amplifier for the given channel.

8. A method of suppressing crosstalk between adjacent channels in a multichannel IC amplifier, comprising:

providing a substrate;

forming a plurality of amplifier circuits on the substrate, each amplifier circuit defining a channel;

forming a pair of inputs for each amplifier circuit; and

coupling each pair of inputs for each amplifier circuit to the amplifier circuit via a pair of capacitors configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels.

9. A multichannel IC amplifier, comprising:

at least first and second amplifier circuits formed on an IC substrate, each amplifier circuit defining a channel and each amplifier circuit coupled to respective inputs via a pair of capacitors, the capacitors being configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels;

wherein the two pair of capacitors comprise a coplanar arrangement of four capacitor plates, each corresponding to a respective DC-blocking capacitor, the four plates respectively corresponding to a left-channel positive-sense capacitor, a left-channel negative-sense capacitor, a right-channel positive-sense capacitor and a right-channel negative-sense capacitor, the plate corresponding to the left-channel positive-sense capacitor and the plate corresponding to the right-channel positive-sense capacitor defining therebetween a first shared edge region having a length U, the plate corresponding to the left-channel negative-sense capacitor and the plate corresponding to the right-channel positive sense capacitor defining therebetween a second shared edge region having a length 2U, and the plate corresponding to the left-channel negative-sense capacitor and the plate corresponding to the right-channel negative-sense capacitor defining therebetween a third shared edge region having a length U.