Sensing scheme of flash EEPROM

• US 6,490,203 B1
• Filed: 05/24/2001
• Issued: 12/03/2002
• Est. Priority Date: 05/24/2001
• Status: Expired due to Term

• Current Assignee: Esigma Technology Corporation Limited
• Original Assignee: EDN Silicon Devices Incorporated
• Inventors: Tang, Yuan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/863,697
• Publication Number:
  US 20020176281A1
• Time in Patent Office: 558 Days
• Field of Search: 365/185.22, 365/185.2, 365/185.18, 365/185.3, 365/185.29, 365/185.04, 365/185.24, 365/207, 365/210
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.

Claims

1. A reading method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said method comprising the steps of:

applying a fixed control gate bias voltage to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;

charge pumping a power supply potential to generate an output voltage which is higher than the power supply potential;

connecting the output voltage to a resistor-divider network;

generating from the resistor-network a first one of the varied control gate bias voltages which corresponds to the program verify mode of operation, a second one of the varied control gate bias voltages which corresponds to the erase verify mode of operation, and a third one of the varied control gate bias voltages which corresponds to the over-erase-correction mode of operation;

applying from a multiplexer either the first one, the second one, or the third one of the varied control gate bias voltages to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations; and

comparing a sensed voltage corresponding to the core cell drain current and a references voltage corresponding to one of said different reference currents and generating an output signal which is at a high logic when said sensed voltage is less than said reference voltage and which is at a low logic level when said sensed voltage is higher than said reference voltage.

2. The reading method for performing program verify, erase verify, and over-erase-correction modes of operations as claimed in claim 1, wherein said reference cell transistor has its threshold voltage programmed to be substantially equal to a neutral threshold voltage so as to be very stable.

3. The reading method for performing program verify, erase verify, and over-erase-correction modes of operations as claimed in claim 1, wherein the step of comparing includes receiving sensed voltage on an inverting input of a high gain amplifier, receiving said reference voltage on a non-inverting input of the high gain amplifier, and generating said output signal on an output of the high gain amplifier.

4. A reading circuit for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said circuit comprising:

means for generating a fixed control gate bias voltage to be applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;

means for generating varied control gate bias voltages to be applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations;

said means for generating the varied control gate bias voltages including reference bias generator means formed of a charge pump circuit generating an output voltage, a resistor-divider network having its one end connected to the output voltage and its other end connected to a ground potential, and a multiplexer;

said resistor-divider network providing a first one of the varied control gate bias voltages which corresponds to the program verify mode of operation, a second one of the varied control gate bias voltages which corresponds to the erase verify mode of operation, and a third one of the varied control gate bias voltages which corresponds to the over-erase-correction mode of operation;

said multiplexer being responsive to a verify mode control signal for generating either the first one, the second one, or the third one of said varied control gate bias voltages; and

means for comparing a sensed voltage corresponding to the core cell drain current and a reference voltage corresponding to one of said different reference currents and for generating an output signal which is at a high logic when said sensed voltage is less than said reference voltage and which is at a low logic level when said sensed voltage is higher than said reference voltage.

5. The reading circuit for performing program verify, erase verify, and over-erase-correction modes of operations as claimed in claim 4, wherein said reference cell transistor has its threshold voltage programmed to be substantially equal to a neutral threshold voltage so as to be very stable.

6. The reading circuit for performing program verify, erase verify, and over-erase-correction modes of operations as claimed in claim 4, wherein said comparing means includes a high gain amplifier having an inverting input for receiving said sensed voltage, a non-inverting input for receiving said reference voltage, and an output for providing said output signal.

7. A reading circuit for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells, said circuit comprising:

means for generating a fixed control gate bias voltage to be applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current;

current source circuit means for generating different reference currents corresponding to predetermined modes of operations;

said current source circuit means for generating the different reference currents including a current mirror arrangement formed of a first N-channel transistor and a second N-channel transistor, a parallel-connected resistor network formed of a plurality of resistors whose values are pre-set so as to be very stable, and a multiplexer;

one end of each of the plurality of resistors being connected to a power supply potential and its other end being connected to a respective input of said multiplexer;

said multiplexer having its output connected to said current mirror arrangement for generating either a first one of said different reference currents which corresponds to the program verify mode of operation, a second one of said different reference currents which corresponds to the erase mode of operation, or a third one of said different reference currents which corresponds to the over-erase-correction operation; and

comparing the core cell drain current and one of said different reference currents and generating an output signal which is at a high logic when the core cell drain current is higher than said one of said different reference currents and which is at a low logic level when the core cell drain current is lower than said one of said different reference currents.