Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness

• US 6,490,210 B2
• Filed: 05/31/2001
• Issued: 12/03/2002
• Est. Priority Date: 06/07/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takase, Satoru, Nagai, Takeshi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/867,796
• Publication Number:
  US 20010050871A1
• Time in Patent Office: 551 Days
• Field of Search: 365/200, 365/201, 365/230.09, 365/230.04, 365/230.06, 365/230.03
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a memory cell array having a plurality of normal signal lines for selecting a memory cell, a redundant cell array including three or more of odd number of spare signal lines for compensating for defectiveness in the memory cell array, a decoder for decoding an address signal to select a normal signal line, a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line, and a test control circuit for controlling the decoder and the spare decoder to perform a test of applying voltage between adjacent signal lines in the normal signal lines and the spare signal lines. The test control circuit sets electric potential levels in a signal line group including the normal signal lines and the spare signal lines so that at the time of a test, electric potential levels of adjacent signal lines are opposite to each other.

Claims

1. A semiconductor memory integrated circuit comprising:

a memory cell array in which a plurality of normal signal lines for selecting a memory cell are arranged;

a redundant cell array in which three or more of odd number of spare signal lines for compensating for defectiveness in said memory cell array are arranged;

a decoder for decoding an address signal to select a normal signal line;

a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line; and

a test control circuit for controlling said decoder and said spare decoder to carry out a test of applying a voltage between adjacent lines in said normal signal lines and said spare signal lines,

at the time of performing the test, said test control circuit setting potential levels in a signal line group including said normal signal lines and said spare signal lines so that a plurality of signal lines included in said signal line group are turned active simultaneously and potential levels of two adjacent signal lines are opposite to each other.

2. The semiconductor memory integrated circuit according to claim 1, wherein a wiring line having a fixed electric potential is provided in said odd number of spare signal lines, and at the time of performing the test, said wiring line is used as a pseudo signal line included in said signal line group.

3. The semiconductor memory integrated circuit according to claim 1, wherein said memory cell array is divided into sections which are provided on both sides of said redundant cell array, and said normal signal lines, which are provided on both sides of said spare signal lines in said redundant cell array, are assigned sequential addresses.

4. The semiconductor memory integrated circuit according to claim 1, wherein said redundant cell array is a redundant column cell array, and said normal signal lines and said spare signal lines are column selecting lines and spare column selecting lines, respectively, for performing a bit line selection in said memory cell array and said redundant column cell array.

5. The semiconductor memory integrated circuit according to claim 1, wherein:

said memory cell array is divided into sub cell arrays, which are provided on both sides of said redundant cell array;

at the time of a normal operation, said normal signal lines, which are provided on both sides of said spare signal lines in said redundant cell array, are assigned addresses so that even-numbered addresses and odd-numbered addresses are alternately and successively assigned; and

at the time of the test, the arrangement order of even-numbered addresses and odd-numbered addresses is reversed for said normal signal lines provided on both sides of said spare signal lines of said redundant cell array.

6. The semiconductor memory integrated circuit according to claim 5, wherein:

said redundant cell array is divided into sections each including an odd number of spare lines, which are provided on both sides of said sub cell arrays; and

said spare signal lines, which are provided on both sides of said sub cell arrays, are assigned sequential addresses.

7. The semiconductor memory integrated circuit according to claim 1, wherein at the time of performing a test, said test control circuit sets potential levels of said normal signal lines and said spare signal lines in said signal group so that potential levels of two adjacent signal lines are opposite to each other, by alternately assigning even-numbered addresses and odd-numbered addresses.

8. The semiconductor memory integrated circuit according to claim 7, wherein:

said memory cell array is divided into a plurality of sub cell arrays;

a plurality of said redundant cell arrays each having an odd number of spare signal lines are provided so that a sub cell array is adjacent to a redundant cell array;

at the time of a normal operation, said normal signal lines in said memory cell array and said spare signal lines in said redundant cell arrays are assigned addresses so that even-numbered addresses and odd-numbered addresses are alternately and successively assigned; and

at the time of the test, the arrangement order of even-numbered addresses and odd-numbered addresses in at least one of said redundant cell arrays is reversed so that potential levels of two adjacent signal lines in said signal group are opposite to each other.

9. A semiconductor memory integrated circuit comprising:

a memory cell array in which a plurality of normal signal lines for selecting a memory cell are arranged;

a redundant cell array in which three or more of odd number of spare signal lines for compensating for defectiveness in said memory cell array are arranged;

a decoder for decoding an address signal to select a normal signal line;

a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line; and

a test control circuit for controlling said decoder and said spare decoder to carry out a test of applying a voltage between adjacent lines in said normal signal lines and said spare signal lines,

at the time of performing the test, said test control circuit assigning addresses to said signal lines included in a signal line group having said normal signal lines and said spare signal lines so that even-numbered addresses and odd-numbered addresses are alternately assigned.

10. The semiconductor memory integrated circuit according to claim 9, wherein a wiring line having a fixed electric potential is provided in said odd number of spare signal lines, and at the time of performing the test, said wiring line is used as a pseudo signal line included in said signal line group.

11. The semiconductor memory integrated circuit according to claim 9, wherein said memory cell array is divided into sections which are provided on both sides of said redundant cell array, and said normal signal lines, which are provided on both sides of said spare signal lines in said redundant cell array, are assigned sequential addresses.

12. The semiconductor memory integrated circuit according to claim 9, wherein said redundant cell array is a redundant column cell array, and said normal signal lines and said spare signal lines are column selecting lines and spare column selecting lines, respectively, for performing a bit line selection in said memory cell array and said redundant column cell array.

13. The semiconductor memory integrated circuit according to claim 9, wherein:

said memory cell array is divided into sub cell arrays, which are provided on both sides of said redundant cell array;

at the time of a normal operation, said normal signal lines, which are provided on both sides of said spare signal lines in said redundant cell array, are assigned addresses so that even-numbered addresses and odd-numbered addresses are alternately and successively assigned; and

at the time of the test, the arrangement order of even-numbered addresses and odd-numbered addresses is reversed for said normal signal lines provided on both sides of said spare signal lines of said redundant cell array.

14. The semiconductor memory integrated circuit according to claim 13, wherein:

said redundant cell array is divided into sections each including

an odd number of spare lines, which are provided on both sides of said sub cell arrays; and

said spare signal lines, which are provided on both sides of said sub cell arrays, are assigned sequential addresses.

15. The semiconductor memory integrated circuit according to claim 9, wherein:

said memory cell array is divided into a plurality of sub cell arrays;

a plurality of said redundant cell arrays each having an odd number of spare signal lines are provided so that a sub cell array is adjacent to a redundant cell array;

at the time of a normal operation, said normal signal lines in said memory cell array and said spare signal lines in said redundant cell arrays are assigned addresses so that even-numbered addresses and odd-numbered addresses are alternately and successively assigned; and

at the time of the test, the arrangement order of even-numbered addresses and odd-numbered addresses in at least one of said redundant cell arrays is reversed so that potential levels of two adjacent signal lines in said signal group are opposite to each other.

16. A method for testing a semiconductor memory device, the method comprising:

assigning a unique first address to at least some of each of a plurality of signal lines in a normal mode, the plurality of signal lines including normal signal lines and spare signal lines; and

assigning, in test mode, a second address to at least one of the plurality of signal lines, the second address being either odd-numbered when the first address is even-numbered or even-numbered when the first address is odd-numbered.

17. The method of claim 16, further including simultaneously applying a voltage stress between each adjacent signal line in the plurality of signal lines.

18. The method of claim 16, wherein the plurality of signal lines alternate between even numbered and odd numbered addresses.

19. The method of claim 16, wherein the semiconductor memory device includes a fixed-potential line having a potential corresponding to a logic level disposed between two of the plurality of signal lines, the two of the plurality of signal lines each being assigned an even address in the test mode, the method further including the step of simultaneously applying a same logic level as the fixed-potential line to each of the plurality of signal lines that have an odd address in the test mode.

20. The method of claim 19, wherein the plurality of signal lines on a first side of the fixed-potential line have alternating even and odd addresses in the test mode, and the plurality of signal lines on an opposing side of the fixed-potential line have alternating even and odd addresses in the test mode.

21. The method of claim 16, wherein the semiconductor memory device includes a fixed-potential line having a potential corresponding to a logic level disposed between two of the plurality of signal lines, the two of the plurality of signal lines each being assigned an odd address in the test mode, the method further including the step of simultaneously applying a same logic level as the fixed-potential line to each of the plurality of signal lines that have an even address in the test mode.

22. The method of claim 21, wherein the plurality of signal lines on a first side of the fixed-potential line have alternating even and odd addresses in the test mode, and the plurality of signal lines on an opposing side of the fixed-potential line have alternating even and odd addresses in the test mode.

23. A semiconductor memory integrated circuit having a group of signal lines, comprising:

a memory cell array having a plurality of normal signal lines as part of the group of signal lines, each having a unique first address;

a redundant cell array having an odd plurality of spare signal lines as part of the group of signal lines; and

a circuit configured to assign a second address to at least one of the signal lines of the group of signal lines, the second address being either odd-numbered when the first address is even-numbered or even-numbered when the first address is odd-numbered, and to apply a voltage stress between each adjacent signal line of the group of signal lines.

24. A decoder comprising:

a normal mode circuit for selecting a signal line during normal operation;

a test mode circuit coupled to said normal mode circuit and configured to simultaneously select every other one of a plurality of signal lines, the plurality of signal lines including a plurality of normal signal lines and an odd plurality of spare signal lines.