Multi-link segmentation and reassembly for bonding multiple PVC's in an inverse multiplexing arrangement

• US 6,490,296 B2
• Filed: 10/10/2001
• Issued: 12/03/2002
• Est. Priority Date: 02/28/2001
• Status: Expired due to Fees

• Current Assignee: Atwater Partners of Texas LLC
• Original Assignee: Symmetricom Incorporated (Microchip Technology Incorporated)
• Inventors: Yang, Jining, Shenoi, Kishan, Jacobsen, Gary, Kraba, Kamila, Lai, Chien-Chou, Sommer, Jeremy
• Primary Examiner(s): Marcelo, Melvin
• Assistant Examiner(s): MEHRA, INDER P
• Application Number:
  US09/974,177
• Publication Number:
  US 20020146010A1
• Time in Patent Office: 419 Days
• Field of Search: 370/236, 370/394, 370/395.41, 370/395.42, 370/397, 370/399, 370/412, 370/428, 370/469, 370/474
• US Class Current: 370/469
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04L 2012/565 Sequence integrity
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 45/10 Routing in connection-oriented networks, e.g. X.25 or ATM
• CPC Class Codes: H04L 45/24 Multipath
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/125 by balancing the load, e.g. traffic engineering
• CPC Class Codes: H04L 47/16 in connection oriented networks, e.g. frame relay
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/43 Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits in an inverse multiplexing arrangement. A method includes: generating a plurality of multilink segmentation and reassembly sublayer cells at a first location; distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits; transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer; a multilink controller coupled to the source buffer; and a plurality of virtual circuits coupled to the multilink controller.

Claims

1. A method, comprising:

generating a plurality of multilink segmentation and reassembly sublayer cells at a first location;

distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits;

transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and

receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location.

2. The method of claim 1, wherein generating thee plurality of multilink segmentation and reassembly sublayer cells includes providing each of a plurality of asymmetric transfer mode information cells with a multilink segmentation and reassembly sublayer identifier.

3. The method of claim 1, wherein generating the plurality of multilink segmentation and reassembly sublayer cells includes providing each of the plurality of asymmetric transfer mode information cells with a multilink segmentation and reassembly sequence number.

4. The method of claim 1, wherein distributing the plurality of multilink segmentation and reassembly sublayer cells across the plurality of virtual circuits includes monitoring a virtual circuit buffer status for each of a plurality of virtual circuit buffers.

5. The method of claim 1, wherein distributing the plurality of multilink segmentation and reassembly sublayer cells includes selecting a virtual circuit in which the virtual circuit buffer status indicates a fill level below a low level.

6. The method of claim 1, wherein distributing the plurality of multilink segmentation and reassembly sublayer cells includes waiving a virtual circuit in which the virtual circuit buffer status indicates a fill level above a high level.

7. The method of claim 1, wherein distributing the plurality of multilink segmentation and reassembly sublayer cells includes selecting a virtual circuit in which the virtual circuit buffer status indicates a fill level between the low level and the high level.

8. The method of claim 1, wherein receiving the plurality of multilink segmentation and reassembly sublayer cells includes aggregating the plurality of multilink segmentation and reassembly sublayer cells.

9. The method of claim 8, wherein aggregating the plurality of multilink segmentation and reassembly sublayer cells includes arranging the plurality of multilink segmentation and reassembly sublayer cells in a particular order defined by a plurality of multilink segmentation and reassembly sublayer sequence numbers.

10. The method of claim 9, wherein arranging the plurality of multilink segmentation and reassembly sublayer cells includes writing the plurality of multilink segmentation and reassembly sublayer cells into a double buffer arrangement.

11. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 1.

12. An apparatus for performing the method of claim 1.

13. An electronic media, comprising a program for performing the method of claim 1.

14. A method, comprising converting a cell into a multilink segmentation and reassembly sublayer format, including:

receiving an asymmetric transfer mode network cell from a conventional segmentation and reassembly sublayer mechanism;

writing the asymmetric transfer mode network cell to a memory buffer;

reading a plurality of octets from the memory buffer;

appending a multilink segmentation and reassembly sublayer identifier and a multilink segmentation and reassembly sublayer sequence number to the plurality of octets forming a multilink segmentation and reassembly sublayer cell;

transmitting the multilink segmentation and reassembly sublayer cell to a virtual circuit controller;

appending a plurality of header octets to the multilink segmentation and reassembly sublayer cell; and

transmitting the multilink segmentation and reassembly sublayer cell via a virtual circuit.

15. The method of claim 14, further comprising receiving another asymmetric transfer mode network cell from the conventional segmentation and reassembly sublayer mechanism.

16. The method of claim 14, wherein writing the asymmetric transfer mode network cell to a memory buffer includes writing the asymmetric transfer mode network cell to a memory buffer utilizing a memory write controller.

17. The method of claim 16, wherein utilizing a memory write controller includes utilizing a write address pointer.

18. The method of claim 14, wherein reading the plurality of octets from a memory buffer includes reading the plurality of octets from a memory buffer utilizing a memory read controller.

19. The method of claim 18, wherein utilizing a memory read controller includes utilizing a read address pointer.

20. The method of claim 14, further comprising:

utilizing the memory write address pointer to select an address in the memory buffer to be written;

utilizing the memory read address pointer to select an address in the memory buffer to be read;

allowing the memory read controller to read a plurality of octets from the memory buffer if the write address pointer is ahead of the read address pointer at least a number of addresses equal to the number of bytes of a multilink segmentation and reassembly sublayer cell; and

detecting an error condition if the memory read address pointer overtakes the memory write address pointer.

21. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 14.

22. An apparatus for performing the method of claim 14.

23. An electronic media, comprising a program for performing the method of claim 14.

24. A method, comprising converting plurality of multilink segmentation and reassembly sublayer cells into an asymmetric transfer mode format, including:

receiving a plurality multilink segmentation and reassembly sublayer cells from a plurality of virtual circuits;

writing the plurality of multilink segmentation and reassembly sublayer cells to a memory buffer in a sequence defined by a plurality of multilink segmentation and reassembly sublayer sequence numbers;

reading a plurality of octets from the memory buffer;

assembling the plurality of octets into a plurality of asymmetric transfer mode cells; and

transmitting the plurality of asymmetric transfer mode cells to a conventional segmentation and reassembly sublayer mechanism.

25. The method of claim 24, wherein writing the plurality of multilink segmentation and reassembly sublayer cells to a memory buffer includes writing the plurality of multilink segmentation and reassembly sublayer cells to a memory buffer utilizing a memory write controller.

26. The method of claim 25, wherein utilizing a memory write controller includes utilizing a write address pointer.

27. The method of claim 25, wherein utilizing a memory write controller includes utilizing a memory write controller to put the plurality of multilink segmentation and reassembly sublayer cells in a sequence determined by a plurality of multilink segmentation and reassembly sublayer cell sequence numbers.

28. The method of claim 24, wherein reading the plurality of octets from a memory buffer includes reading the plurality of octets from a memory buffer utilizing a memory read controller.

29. The method of claim 28, wherein utilizing a memory read controller includes utilizing a read address pointer.

30. The method of claim 24, further comprising:

utilizing the memory write address pointer to select an address in the memory buffer to be written;

utilizing the memory read address pointer to select an address in the memory buffer to be read;

allowing the memory read controller to read a plurality of octets from the memory buffer if the write address pointer is ahead of the read address pointer at least a number of addresses equal to the number of bytes of an asymmetric transfer mode cell; and

detecting an error condition if the memory read address pointer overtakes the memory write address pointer.

31. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 24.

32. An apparatus for performing the method of claim 24.

33. An electronic media, comprising a program for performing the method of claim 24.

34. An apparatus, comprising a multilink segmentation and reassembly sublayer transmitter, including:

a source buffer;

a multilink controller coupled to the source buffer; and

a plurality of virtual circuits coupled to the multilink controller.

35. The apparatus of claim 34, wherein the source buffer includes a source first-in-first-out buffer.

36. The apparatus of claim 34, wherein each of the plurality of virtual circuits include:

a virtual circuit buffer coupled to the multilink controller;

a physical layer control mechanism coupled to the virtual circuit buffer; and

a digital subscriber line pipe coupled to the physical layer control mechanism.

37. The apparatus of claim 36, wherein the virtual circuit buffer includes a virtual circuit first-in-first-out buffer.

38. The apparatus of claim 34, wherein the multilink controller receives a source buffer fill-status line from the source buffer.

39. The apparatus of claim 34, wherein the multilink controller receives a virtual circuit buffer fill-status line from the virtual circuit buffer.

40. An apparatus, comprising a multilink segmentation and reassembly sublayer receiver, including:

a plurality of virtual circuits;

a multilink controller coupled to the plurality of virtual circuits;

a plurality of intermediate buffers coupled to the multilink controller; and

a receive buffer coupled to the plurality of intermediate buffers.

41. The apparatus of claim 40, wherein the receive buffer includes a source first-in-first-out buffer.

42. The apparatus of claim 40, wherein each of the plurality of virtual circuits include:

a digital subscriber line pipe;

a physical layer control mechanism coupled to the digital subscriber pipe; and

a virtual circuit buffer coupled to the physical layer and to the multilink controller.

43. The apparatus of claim 42, wherein the virtual circuit buffer includes a virtual circuit first-in-first-out buffer.

44. The apparatus of claim 40, wherein the plurality of intermediate buffers includes a pair of intermediate buffers.

46. The apparatus of claim 40, wherein the memory buffer includes a circular memory buffer of size 1104 bytes.

45. An apparatus, comprising a segmentation and reassembly sublayer converter, including:

a segmentation and reassembly sublayer mechanism;

a memory write controller coupled to the segmentation and reassembly sublayer mechanism;

a memory buffer coupled to the memory write controller;

a memory read controller coupled to the memory buffer; and

a virtual circuit controller coupled to the memory read controller.