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Data processing apparatus and method for cache line replacement responsive to the operational state of memory

  • US 6,490,655 B1
  • Filed: 09/13/1999
  • Issued: 12/03/2002
  • Est. Priority Date: 01/19/1999
  • Status: Expired due to Term
First Claim
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1. Data processing apparatus comprising:

  • (i) a cache memory having a plurality of cache storage lines;

    (ii) a plurality of main memory units operable to store data words to be cached within said cache memory; and

    (iii) a cache victim select circuit for selecting a victim cache storage line into which one or more data words are to be transferred from one of said main memory units following a cache miss;

    wherein (iv) said cache victim select circuit is responsive to an operational state of at least one of said main memory units when selecting said victim cache storage line.

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