Generation of sub-netlists for use in incremental compilation

• US 6,490,717 B1
• Filed: 08/15/2000
• Issued: 12/03/2002
• Est. Priority Date: 10/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Khalaf, Marwan Adel, Pedersen, Bruce, Heile, Francis B., Mendel, David Wolk
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/639,657
• Time in Patent Office: 840 Days
• Field of Search: 716/1, 716/2, 716/3, 716/6, 716/11, 716/12, 716/18
• US Class Current: 716/104
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
• CPC Class Codes: G06Q 10/10 Office automation; Time management
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management

Abstract

A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a “sub-netlist” within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer'"'"'s changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

Claims

1. In a compiler that compiles an electronic design for implementation on a target hardware device, a method of identifying a changed portion of a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and the changed portion which is changed from the original electronic design, the method comprising:

(a) identifying one or more new logic nodes in an unsynthesized representation of the changed electronic design that have been directly changed from the original electronic design;

(b) tracing a signal propagation path between at least one of the new logic nodes and one or more external nodes, which external nodes include hard registers and I/O pins, such that nodes encountered on the signal propagation path are designated as affected nodes;

wherein the changed portion of the changed electronic design includes both the new logic nodes and the affected nodes;

(c) synthesizing the changed portion of the changed electronic design;

(d) incorporating the synthesized changed portion in a synthesized netlist of the original design to produce the changed electronic design; and

(e) mapping the changed electronic design into logic cells corresponding to portions of the target hardware device.

2. The method of claim 1, wherein tracing a signal propagation path comprises tracing a path forward from an output of a new logic node to one or more external nodes.

3. The method of claim 1, wherein tracing a signal propagation path comprises tracing a path backward from an input of a new logic node to one or more external nodes.

4. The method of claim 1, further comprising:

comparing an unsynthesized netlist of the changed electronic design with a synthesized netlist of the original electronic design to identify as external nodes those hard registers and I/O pins which are (i) common between the unsynthesized netlist and the synthesized netlist and (ii) output a common signal.

5. The method of claim 1, wherein the target hardware device is an Application Specific Integrated Circuit.

6. The method of claim 5, wherein the target hardware device is a Programmable Logic Device.

7. A machine readable medium containing instructions for operating a compiler that compiles an electronic design for implementation on a target hardware device,

the instructions controlling identification of a changed portion of a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and the changed portion which is changed from the original electronic design, the instructions specifying operations comprising:

(a) identifying one or more new logic nodes in the changed electronic design that have been directly changed from the original electronic design;

(b) tracing a signal propagation path between at least one of the new logic nodes and one or more external nodes, which external nodes include hard registers and I/O pins, such that nodes encountered on the signal propagation path are designated as affected nodes;

wherein the changed portion of the changed electronic design includes both the new logic nodes and the affected nodes;

(c) synthesizing the changed portion of the changed electronic design;

(d) incorporating the synthesized changed portion in a synthesized netlist of the original design to produce the changed electronic design; and

(e) mapping the changed electronic design into logic cells corresponding to portions of the target hardware device.

8. The machine readable medium of claim 7, wherein the instructions specify that tracing a signal propagation path comprises tracing a path forward from an output of a new logic node to one or more external nodes.

9. The machine readable medium of claim 7, wherein instructions specify that tracing a signal propagation path comprises tracing a path backward from an input of a new logic node to one or more external nodes.

10. The machine readable medium of claim 7, wherein the instructions further comprise:

comparing an unsynthesized netlist of the changed electronic design with a synthesized netlist of the original electronic design to identify as external nodes those hard registers and I/O pins which are (i) common between the unsynthesized netlist and the synthesized netlist and (ii) output a common signal.

11. In a compiler that compiles an electronic design for implementation on a target hardware device, a method of incrementally recompiling a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and a changed portion which is changed from the original electronic design, the method comprising:

(a) identifying new nodes appearing in the changed electronic design but not in the original electronic design;

(b) identifying external nodes, which are hard registers and I/O pins common to the changed electronic design and the original electronic design;

(c) in the changed electronic design, tracing a forward signal propagation path from the new nodes to the first external nodes encountered on the forward signal propagation path;

(d) in the changed electronic design;

tracing a backward signal propagation path from the first external nodes to the next external nodes encountered on the backward signal propagation path, thereby identifying any nodes encountered on the backward signal propagation path as included in the changed portion of the changed electronic design;

(e) inserting the changed portion into the original electronic design; and

(f) incrementally compiling the changed portion within the original electronic design.

12. The method of claim 11, further comprising:

(i) in the original electronic design, tracing backward from the first external nodes until encountering further external nodes; and

(ii) during (e), replacing any nodes in the original design encountered while tracing backward as with the changed portion of the original electronic design.

13. The method of claim 11, wherein the changed portion of the electronic design comprises, the first external nodes, the next external nodes, in addition to any nodes encountered on the backward signal propagation path.

14. The method of claim 13, further comprising:

(i) in the original electronic design, tracing backward from the first external nodes until encountering further external nodes; and

(ii) during (e), replacing the first external nodes, the further external nodes, together with any nodes in the original design encountered while tracing backward as with the changed portion of the original electronic design.

15. The method of claim 11, wherein the changed portion of the changed electronic design is provided as at least part of a netlist.

16. The method of claim 15, wherein the netlist is unsynthesized.

17. The method of claim 13, further comprising:

(i) synthesizing the changed portion of the changed electronic design to produce a synthesized changed portion;

(ii) during (e), incorporating the synthesized changed portion in a synthesized netlist of the original design.

18. The method of claim 11, wherein the target hardware device is an Application Specific Integrated Circuit.

19. The method of claim 18, wherein the target hardware device is a Programmable Logic Device.

20. A computer program product comprising a machine readable medium on which is provided instructions for operating a compiler that compiles an electronic design for implementation on a target hardware device,

the instructions controlling incrementally recompiling a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and a changed portion which is changed from the original electronic design, the instructions specifying operations comprising:

(a) identifying new nodes appearing in the changed electronic design but not in the original electronic design;

(b) identifying external nodes, which are hard registers and I/O pins common to the changed electronic design and the original electronic design;

(c) in the changed electronic design, tracing a forward signal propagation path from the new nodes to the first external nodes encountered on the forward signal propagation path;

(d) in the changed electronic design;

tracing a backward signal propagation path from the first external nodes to the next external nodes encountered on the backward signal propagation path, thereby identifying any nodes encountered on the backward signal propagation path as included in the changed portion of the changed electronic design;

(e) inserting the changed portion into the original electronic design; and

(f) incrementally compiling the changed portion within the original electronic design.

21. The computer program product of claim 20, further comprising instructions for the following operations:

(i) in the original electronic design, tracing backward from the first external nodes until encountering further external nodes; and

(ii) during (e), replacing any nodes in the original design encountered while tracing backward as with the changed portion of the original electronic design.

22. The computer program product of claim 20, wherein the changed portion of the electronic design comprises, the first external nodes, the next external nodes, in addition to any nodes encountered on the backward signal propagation path.

23. The computer program product of claim 22, further comprising instructions for the following operations:

(i) in the original electronic design, tracing backward from the first external nodes until encountering further external nodes; and

(ii) during (e), replacing the first external nodes, the further external nodes, together with any nodes in the original design encountered while tracing backward as with the changed portion of the original electronic design.

24. The computer program product of claim 20, wherein the changed portion of the changed electronic design is provided as at least part of a netlist.

25. The computer program product of claim 24, wherein the netlist is unsynthesized.

26. The computer program product of claim 25, further comprising instructions for the following operations:

(i) synthesizing the changed portion of the changed electronic design to produce a synthesized changed portion;

(ii) during (e), incorporating the synthesized changed portion in a synthesized netlist of the original design.

27. The computer program product of claim 20, wherein the target hardware device is an Application Specific Integrated Circuit.

28. The computer program product of claim 27, wherein the target hardware device is a Programmable Logic Device.