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Generation of sub-netlists for use in incremental compilation

  • US 6,490,717 B1
  • Filed: 08/15/2000
  • Issued: 12/03/2002
  • Est. Priority Date: 10/28/1996
  • Status: Expired due to Term
First Claim
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1. In a compiler that compiles an electronic design for implementation on a target hardware device, a method of identifying a changed portion of a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and the changed portion which is changed from the original electronic design, the method comprising:

  • (a) identifying one or more new logic nodes in an unsynthesized representation of the changed electronic design that have been directly changed from the original electronic design;

    (b) tracing a signal propagation path between at least one of the new logic nodes and one or more external nodes, which external nodes include hard registers and I/O pins, such that nodes encountered on the signal propagation path are designated as affected nodes;

    wherein the changed portion of the changed electronic design includes both the new logic nodes and the affected nodes;

    (c) synthesizing the changed portion of the changed electronic design;

    (d) incorporating the synthesized changed portion in a synthesized netlist of the original design to produce the changed electronic design; and

    (e) mapping the changed electronic design into logic cells corresponding to portions of the target hardware device.

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