Etching method for production of semiconductor devices

• US 6,492,068 B1
• Filed: 01/07/2000
• Issued: 12/10/2002
• Est. Priority Date: 01/12/1999
• Status: Expired due to Fees

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Suzuki, Koji
• Primary Examiner(s): GOUDREAU, GEORGE A
• Application Number:
  US09/478,789
• Time in Patent Office: 1,068 Days
• Field of Search: 438/725, 438/714, 438/736, 430/5
• US Class Current: 430/5
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks

Abstract

An etching method for use in production of semiconductor devices is disclosed. In the etching method, CBr_x or its derivative formed in the plasma is deposited on portions of the surface of a substrate to be etched. A sidewall and/or underlying layer protection effect is obtained concurrently with an improved resist selectivity through the function of the high boiling point of the deposit.

Claims

1. A method for forming a gate electrode of a semiconductor device, comprising:

providing a semiconductor substrate having a stack of a resist mask layer, an organic coating layer, a conductive material layer, and a gate dielectric layer, the resist mask layer including a resist mask pattern partially masking the organic coating layer;

etching the organic coating layer through the resist mask layer using an etching gas atmosphere including O₂, Cl₂, and HBr to form a pattern of the organic coating corresponding with the resist mask pattern, the etching including controllably reducing a width of the resist mask pattern such that a width of the pattern of the organic coating is determined by the reduced width of the resist mask pattern; and

patterning the conductive material layer by etching through the pattern of the organic material, wherein;

the mask pattern includes an isolated mask pattern having a first lateral mask dimension before the etching and a densely arranged mask pattern having a second lateral mask dimension before the etching;

the pattern of the organic coating includes an isolated pattern corresponding with the isolated mask pattern and a densely arranged pattern corresponding with the densely arranged mask pattern; and

the etching is performed such that the isolated pattern has a first lateral dimension, the densely arranged pattern has a second lateral dimension, and a first difference between the first lateral dimension of the pattern and the first lateral dimension of the mask pattern is substantially identical to a second difference between the second lateral dimension of the pattern and the second lateral dimension of the mask pattern.

2. The method according to claim 1, wherein the etching comprises an overetching, an amount of the overetching is selected to control the first difference and the second difference.

4. The method according to claim 1, wherein the conductive material layer includes a polycrystalline silicon layer.

5. The method according to claim 1, wherein the organic coating layer is a bottom anti-reflection coating layer.

12. The method according to claim 1, wherein a ratio of O₂ and Cl₂ in the etching gas atmosphere is selected so that the first difference is substantially identical to the second difference.

3. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having an organic material layer thereon and a mask layer having a mask pattern partially masking the organic material layer; and

etching the organic material layer through the mask layer using an etching gas atmosphere including O₂, Cl₂, and HBr to form a pattern of the organic material layer corresponding with the mask pattern, the etching including controllably reducing a lateral dimension of the pattern, wherein;

the mask pattern includes an isolated mask pattern having a first lateral mask dimension before the etching and a densely arranged mask pattern having a second lateral mask dimension before the etching;

the pattern of the organic coating includes an isolated pattern corresponding with the isolated mask pattern and a densely arranged pattern corresponding with the densely arranged mask pattern; and

the etching is performed such that the isolated pattern of the organic material layer has a first lateral dimension, the densely arranged pattern of the organic material layer has a second lateral dimension, and a first difference between the first lateral dimension of the pattern and the first lateral dimension of the mask is substantially identical to a second difference between the second lateral dimension of the pattern and the second lateral dimension of the mask.

6. The method according to claim 3, wherein a ratio of O₂ and Cl₂ in the etching gas atmosphere is selected so that the first difference is substantially identical to the second difference.

7. The method according to claim 3, wherein the isolated pattern includes sidewalls that have a first angle, and the densely arranged pattern includes sidewalls that have a second angle that is substantially identical to the first angle.

13. The method according to claim 3, wherein the etching comprises an overetching, an amount of the overetching is selected to control the first difference and the second difference.

8. A method for adjusting a lateral dimension of a resist mask pattern, comprising:

providing a semiconductor substrate having a resist mask layer thereon, the resist mask layer including a resist mask pattern; and

adjusting a lateral dimension of the resist mask pattern by laterally etching the resist with an etching gas atmosphere including O₂, Cl₂, and HBr, wherein;

the resist mask pattern includes an isolated mask pattern and a densely arranged mask pattern; and

the adjusting comprises laterally etching on the isolated mask pattern by an amount that is substantially identical to an amount of lateral etching on the densely arranged mask pattern.

9. The method according to claim 8, wherein the resist mask pattern includes sidewalls, and an. angle of the sidewalls of the resist mask pattern after the adjusting is substantially identical to the angle of the sidewalls before the adjusting.

10. The method according to claim 8, wherein a ratio of O₂ and Cl₂ in the etching gas atmosphere is selected so that the amount of the lateral etching on the isolated mask pattern is substantially identical to the amount of lateral etching on the densely arranged mask pattern.

11. The method according to claim 8, wherein the isolated mask pattern includes sidewalls that have a first angle after the adjusting, and the densely arranged mask pattern includes sidewalls that have a second angle after the adjusting that is substantially identical to the first angle.

14. A method for adjusting a lateral dimension of a resist mask pattern, comprising:

providing a semiconductor substrate having a conductive material layer thereon, and a resist mask layer over the conductive material layer, the resist mask layer including a resist mask pattern;

adjusting a lateral dimension of the resist mask pattern by laterally etching the resist with an etching gas atmosphere including O₂, Cl₂, and HBr; and

patterning the conductive material layer by etching through the resist mask pattern with the adjusted lateral dimension, wherein;

the resist mask pattern includes an isolated mask pattern and a densely arranged mask pattern; and

the adjusting comprises laterally etching on the isolated mask pattern by an amount that is substantially identical to an amount of lateral etching on the densely arranged mask pattern.