Method of forming a transistor with a strained channel

• US 6,492,216 B1
• Filed: 02/07/2002
• Issued: 12/10/2002
• Est. Priority Date: 02/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Yang, Fu-Liang, Hu, Chenming
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/068,926
• Time in Patent Office: 306 Days
• Field of Search: 438/197, 438/93, 438/105, 438/285, 438/217, 438/172, 438/299
• US Class Current: 438/197
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.

Claims

1. A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of:

forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element;

forming a gate insulator layer overlying said semiconductor alloy layer;

forming a gate structure on said gate insulator layer

forming insulator spacers on sides of said gate structure;

forming source/drain regions in area of said semiconductor alloy layer and in an area of said semiconductor substrate not covered by said gate structure or by said insulator spacers;

removing portions of said semiconductor alloy not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain region; and

forming metal silicide regions on said portions of said semiconductor substrate comprised with said source/drain region.

2. The method of claim 1, wherein said semiconductor alloy layer is a semiconductor alloy comprising of silicon, germanium, and carbon.

3. The method of claim 1, wherein said semiconductor alloy is formed by epitaxial growth procedures.

4. The method of claim 1, wherein said semiconductor alloy layer is obtained by an epitaxial growth of a second semiconductor alloy comprising of silicon and germanium, and implantation of carbon atoms into said second semiconductor alloy.

5. The method of claim 4, wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.

6. The method of claim 4, wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.

7. The method of claim 1, wherein said semiconductor alloy layer is silicon-germanium-carbon layer, denoted as Si₍₁₋

x−

y)Ge_xC_y, wherein x is between 0 to 0.8 and y is between about 0 to 0.04.

8. The method of claim 1, wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.

9. The method of claim 1, wherein said gate insulator layer is a silicon dioxide gate insulator layer.

10. The method of claim 1, wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.

11. A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of:

forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element;

forming a semiconductor capping layer on said semiconductor alloy layer;

forming a gate insulator layer overlying said semiconductor alloy layer;

forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer;

forming insulator spacers on sides of said gate structure;

forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer not covered by said gate structure of by said insulator spacers;

selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and

forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.

12. The method of claim 11, wherein said semiconductor alloy layer is a semiconductor alloy comprising silicon, germanium, and carbon, obtained by epitaxial growth procedures.

13. The method of claim 11, wherein said semiconductor alloy layer is a semiconductor alloy comprising silicon, germanium, and carbon, obtained by epitaxial growth of a second semiconductor alloy comprising of silicon and germanium, and an implantation of carbon atoms into said second semiconductor alloy.

14. The method of claim 11, wherein said semiconductor alloy layer is silicon-germanium-carbon, denoted as Si₍₁₋

x−

y)Ge_xC_y, wherein x is between about 0 to 0.8, and y is between about 0 to 0.04.

15. The method of claim 14, wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.

16. The method of claim 14, wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.

17. The method of claim 11, wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.

18. The method of claim 11, wherein said gate insulator layer is a silicon dioxide gate insulator layer.

19. The method of claim 11, wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.

20. The method of claim 11, wherein said semiconductor capping layer is comprised of silicon.

21. The method of claim 11, wherein said semiconductor capping layer has a final thickness between about 10 to 100 Angstroms.

22. A method of fabricating a semiconductor device on a semiconductor substrate, featuring a strained channel layer, comprising the steps of:

forming isolation regions in a top portion of said semiconductor substrate;

performing a first epitaxial growth procedure to selectively grow a strained channel layer on substantially the portions of said semiconductor substrate not occupied by said isolation regions;

performing a second epitaxial growth procedure to selectively grow a capping layer on said channel layer;

forming a gate insulator layer overlying said capping layer;

forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer;

forming insulator spacers on sides of said gate structure;

forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer, not covered by said gate structure or by said insulator spacers;

selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and

forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.

23. The method of claim 22, wherein said strained channel layer is a semiconductor alloy layer comprising silicon, germanium, and carbon obtained by epitaxial growth procedures.

24. The method of claim 22, wherein said strained channel layer is a semiconductor alloy layer comprising silicon, germanium, and carbon, obtained by epitaxial growth of a second semiconductor alloy comprising silicon and germanium, and an implantation of carbon atoms into said second semiconductor alloy.

25. The method of claim 22, wherein said semiconductor alloy layer is silicon-germanium-carbon, denoted as Si₍₁₋

x−

y)Ge_xC_y, wherein x is between about 0 to 0.8, and y is between about 0 to 0.04.

26. The method of claim 25, wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.

27. The method of claim 25, wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.

28. The method of claim 22, wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.

29. The method of claim 22, wherein said gate insulator layer is a silicon dioxide gate insulator layer.

30. The method of claim 22, wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.

31. The method of claim 22, wherein said semiconductor capping layer is comprised of silicon.

32. The method of claim 22, wherein said semiconductor capping layer has a final thickness between about 10 to 100 Angstroms.