Complementary metal gates and a process for implementation

• US 6,492,217 B1
• Filed: 10/04/2000
• Issued: 12/10/2002
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bai, Gang, Liang, Chunlin
• Primary Examiner(s): Dang, Trung
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US09/679,723
• Time in Patent Office: 797 Days
• Field of Search: 438/199, 438/201, 438/223, 438/217, 438/197, 438/200, 438/224, 438/229, 438/230, 438/231, 438/286, 438/301, 438/305, 257/371, 257/411, 257/410, 257/412
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon

Abstract

A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

Claims

1. A method of forming an integrated circuit device, comprising:

forming a gate dielectric overlying a first region and a second region of a substrate;

forming a barrier layer over the gate dielectric;

depositing a first metal having a first work function over the first region and the second region;

patterning and removing the first metal from a portion of area over the second region;

depositing a second metal having a different second work function over the portion of area over the second region; and

patterning the first metal into a first gate electrode and the second metal into a second gate electrode.

2. The method of claim 1, further comprising:

forming doped first diffusion regions disposed in the substrate adjacent the first gate electrode, such that the work function of the first gate electrode approximates the doping of the first diffusion regions; and

forming doped second diffusion regions disposed in the substrate adjacent the second gate electrode, such that the work function of the second gate electrode approximates the doping of the second diffusion regions.

3. The method of claim 1, wherein the barrier layer is one of undoped polysilicon, titanium nitride, tantalum nitride, and tantalum silicon nitride.

4. The method of claim 1, wherein the work function of the first gate electrode approximates the work function of N-type doped polysilicon and the work function of the second gate electrode approximates the work function of P-type doped polysilicon.

5. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising:

forming a gate dielectric overlying a first region and a second region of a substrate;

forming a barrier layer over the gate dielectric;

depositing a first metal having a first work function over the first region and the second region;

patterning and removing the first metal from a portion of area over the second region;

depositing a second metal having a different second work function over the portion of area over the second region; and

after depositing the first metal and the second metal, patterning the first metal into a first gate electrode and the second metal into a second gate electrode.

6. The method of claim 5, further comprising the step of:

forming doped first diffusion regions disposed in the substrate adjacent the first gate electrode, such that the work function of the first gate electrode approximates the doping of the first diffusion regions; and

forming doped second diffusion regions disposed in the substrate adjacent the second gate electrode, such that the work function of the second gate electrode approximates the doping of the second diffusion regions.

7. The method of claim 5, wherein the barrier layer is one of undoped polysilicon, titanium nitride, tantalum nitride, and tantalum silicon nitride.

8. The method of claim 5, wherein the work function of the first gate electrode approximates work function of N-type doped polysilicon and the work function of the second gate electrode oximates the work function of a P-type doped polysilicon.