×

Methods for edge alignment mark protection during damascene electrochemical plating of copper

  • US 6,492,269 B1
  • Filed: 01/08/2001
  • Issued: 12/10/2002
  • Est. Priority Date: 01/08/2001
  • Status: Active Grant
First Claim
Patent Images

1. A method for fabricating conductive copper interconnects and contact vias comprising:

  • (a) providing a substrate having semiconductor devices with prior alignment marks therein, upon which is an insulating layer;

    (b) forming a patterned conducting layer over the insulating layer;

    (c) depositing a dielectric layer over the patterned conducting layer;

    (d) forming openings in the layer of dielectric aligned to said patterned conducting layer, and forming alignment marks in kerf areas of said substrate;

    (e) placing and positioning a blackout mask over the substrate, protecting the alignment marks;

    (f) depositing by sputtering with the blockout mask in place, a barrier layer and a copper seed layer, over the patterned conducting layer and dielectric layer;

    (g) placing an electroplating copper ring with pin-like extrusions in contact with the substrate, such that the pin-like extrusions cover the alignment marks in kerf areas;

    (h) depositing using the electroplating copper ring with pin-like extrusions, a layer of copper by ECP-Cu electrochemical plating of copper onto and over exposed portions of the copper seed layer;

    (i) removing excess materials by planarization to form inlaid copper interconnects/contact vias, with the alignment marks in place for subsequent processing.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×