Methods for edge alignment mark protection during damascene electrochemical plating of copper

• US 6,492,269 B1
• Filed: 01/08/2001
• Issued: 12/10/2002
• Est. Priority Date: 01/08/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Liu, Chung-Shi, Shue, Shau-Lin, Hsieh, Ching-Hua
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US09/755,570
• Time in Patent Office: 701 Days
• Field of Search: 438/401, 438/633, 438/462, 438/692, 438/687, 438/680, 438/681, 438/671, 438/678, 257/283, 257/793
• US Class Current: 438/687
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to a copper plating method, whereby the wafer edge alignment marks for subsequent processing steps are protected from being covered by copper deposition by two methods: the first method being that of forming alignment mark shields at the wafer'"'"'s edge, thus preventing both barrier and copper seed layers from being deposited in those regions; the second method being that of forming small pad-like extrusions at the contact ring of the copper plating fixture, thus preventing copper plating at the contact points. In the first method, an alignment mark shield Is utilized to cover the alignment mark areas, near the edge of the wafer, with a mechanical shield. This shield protects the alignment mark regions from film deposition during the sputter deposition steps of barrier and copper seed layers. The alignment marks are left without a copper seed layer, hence preventing copper deposition in these regions during copper electroplating. In the second method, the alignment mark areas, near the edge of the wafer, are protected from copper electroplating deposition by use of small pad-like extrusions positioned at copper plating contact ring. The pad-like extrusion is part of the contact ring and prevents copper buildup and deposition on the alignment mark.

Claims

1. A method for fabricating conductive copper interconnects and contact vias comprising:

(a) providing a substrate having semiconductor devices with prior alignment marks therein, upon which is an insulating layer;

(b) forming a patterned conducting layer over the insulating layer;

(c) depositing a dielectric layer over the patterned conducting layer;

(d) forming openings in the layer of dielectric aligned to said patterned conducting layer, and forming alignment marks in kerf areas of said substrate;

(e) placing and positioning a blackout mask over the substrate, protecting the alignment marks;

(f) depositing by sputtering with the blockout mask in place, a barrier layer and a copper seed layer, over the patterned conducting layer and dielectric layer;

(g) placing an electroplating copper ring with pin-like extrusions in contact with the substrate, such that the pin-like extrusions cover the alignment marks in kerf areas;

(h) depositing using the electroplating copper ring with pin-like extrusions, a layer of copper by ECP-Cu electrochemical plating of copper onto and over exposed portions of the copper seed layer;

(i) removing excess materials by planarization to form inlaid copper interconnects/contact vias, with the alignment marks in place for subsequent processing.

2. The method of claim 1, wherein the substrate is selected from the group consisting of:

single crystal Si, Ge or GaAs, or IC module, all having semiconductor devices and prior alignment marks.

3. The method of claim 1, wherein the barrier material consists of TaN deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 100 to 500 Angstroms.

4. The method of claim 1, wherein the copper seed layer material with consists Cu material deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 500 to 2,000 Angstroms.

5. The method of claim 1, wherein the layer of copper consists of copper deposited by ECP-Cu electrochemical plating of copper upon the copper seed layer, in a temperature range of between 20 to 60°

C., and in a thickness range between 3,000 to 15,000 Angstroms.

6. The method of claim 1, wherein conducting wiring can be formed by a dual damascene method, wherein the step of removing the excess materials is selected from the group consisting of planarization by:

chemical mechanical polish (CMP), milling, ion milling, and/or etching.

7. The method of claim 1, wherein the blockout mask is placed and positioned over the substrate, in contact with the substrate, blocking the barrier and seed layer sputter deposition process over the alignment marks.

8. The method of claim 1, in which a electroplating copper ring with pin-like extrusions is positioned over and in contact with the substrate, such that pin-like extrusions cover the alignment marks in kerf areas of said substrate protecting the alignment marks, during a layer of copper deposition by ECP-Cu electrochemical plating of copper, while allowing the layer of copper to plate over the exposed portions of the copper seed layer.

9. The method of claim 1, wherein the layer of dielectric is selected from the group consisting of:

silicon oxide, silicon dioxide, phosphosilicate glass (PSG), fluoro-silicate glass (FSG), deposited by low pressure chemical vapor deposition (LPCVD), a pressure of about 5 Torr, with gases SiH₄ and O₂, and film thickness from 4,000 to 10,000 Angstroms.

10. The method of claim 1, wherein the patterned conducting layer consists of conductively doped polysilicon.

11. The method of claim 1, wherein multilevel conducting structures are fabricated by repeating steps (c) through (i).

12. A method for fabricating conductive copper interconnects and contact vias for applications in MOSFET and CMOS semiconductor devices for trench/via fill applications, protecting alignment marks, comprising:

(a) providing a substrate having semiconductor devices with prior alignment marks therein, upon which is an insulating layer;

(b) forming a patterned conducting layer over the insulating layer;

(c) depositing a layer of dielectric over the patterned conducting layer;

(d) forming openings in the layer of dielectric aligned to said patterned conducting layer, and forming trenches used as alignment marks in kerf areas of said substrate;

(e) placing and positioning a blockout mask over the substrate and trenches, in contact with the substrate, and

(f) depositing by sputter deposition, physical vapor deposition (PVD), with said blockout mask in place, first a barrier layer and then a copper seed layer, over the patterned conducting layer, over the layer of dielectric, while the trenches are protected from the sputter deposition by the blockout mask, filling all openings on the substrate, except over the alignment marks;

(g) depositing a layer of copper by ECP-Cu electrochemical plating of copper onto and over the copper seed layer;

(h) removing excess materials in the copper layer, in the copper seed layer and in the barrier layer by planarization to form inlaid conductive copper interconnects and contact vias, with alignment marks in place for subsequent processing.

13. The method of claim 12, wherein the substrate is selected from the group consisting of:

single crystal Si, Ge or GaAs, or an IC module, all having semiconductor devices and prior alignment marks.

14. The method of claim 12, wherein the barrier material consists of TaN deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 100 to 500 Angstroms.

15. The method of claim 12, wherein the copper seed layer material is selected from the group consisting of Cu material deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 500 to 2,000 Angstroms.

16. The method of claim 12, wherein the layer of copper consists of copper deposited by ECP-Cu electrochemical plating of copper upon with copper seed layer, in a temperature range of between 20 to 60°

C., and in a thickness range between 3,000 to 15,000 Angstroms.

17. The method of claim 12, wherein conducting wiring can be formed by a dual damascene method, wherein the step of removing the excess materials is selected from the group consisting of planarization by:

chemical mechanical polish (CMP), milling, ion milling, and/or etching.

18. The method of claim 12, wherein the blockout mask is placed and positioned over the substrate and trenches, in contact with the substrate, blocking the barrier and seed layer sputter deposition process over the alignment marks.

19. The method of claim 12, wherein the layer of dielectric is selected from the group consisting of:

silicon oxide, silicon dioxide, phosphosilicate glass (PSG), fluoro-silicate glass (FSG), deposited by low pressure chemical vapor deposition (LPCVD), a pressure of about 5 Torr, with gases SiH₄ and O₂, and film thickness from 4,000 to 10,000 Angstroms.

20. The method of claim 12, wherein the patterned conducting layer consists of conductively doped polysilicon.

21. The method of claim 12, wherein multilevel conducting structures are fabricated by repeating steps (c) through (h).

22. A method for fabricating conductive copper interconnects and contact vias for applications in MOSFET and CMOS semiconductor devices for trench/via fill applications, protecting alignment marks, comprising:

(a) providing a substrate having semiconductor devices with prior alignment marks therein, upon which is an insulating layer;

(b) forming a patterned conducting layer over the insulating layer;

(c) depositing a layer of dielectric over the patterned conducting layer;

(d) forming openings in the layer of dielectric aligned to said patterned conducting layer, said layer of dielectric and forming trenches, used as alignment marks in kerf areas of said substrate;

(e) depositing by sputter deposition, physical vapor deposition (PVD), first a barrier layer and then a copper seed layer, over the patterned conducting layer, over the layer of dielectric, filling all openings on the substrate;

(f) placing and positioning a electroplating copper ring with pin-like extrusions over and in contact with the substrate, such that the pin-like extrusions cover the alignment marks in kerf areas of said substrate;

(g) depositing with the electroplating copper ring with pin-like extrusions protecting the alignment marks, a layer of copper by ECP-Cu electrochemical plating of copper onto and over exposed portions of the copper seed layer;

(h) removing excess materials in the copper layer, in the copper seed layer and in the barrier layer by planarization to form inlaid conductive copper interconnects and contact vias, with alignment marks in place for subsequent processing.

23. The method of claim 22, wherein the substrate is selected from the group consisting of:

single crystal Si, Ge or GaAs, or an IC module, all having semiconductor devices and prior alignment marks.

24. The method of claim 22, wherein the barrier material consists of TaN deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 100 to 500 Angstroms.

25. The method of claim 22, wherein the copper seed layer material is selected from the group consisting of Cu material deposited by sputtering, physical vapor deposition (PVD), in a temperature range of between 20 to 300°

C., and in a thickness range between 500 to 2,000 Angstroms.

26. The method of claim 22, wherein the layer of copper consists of copper deposited by ECP-Cu electrochemical plating of copper upon with copper seed layer, in a temperature range of between 20 to 60°

C., and in a thickness range between 3,000 to 15,000 Angstroms.

27. The method of claim 22, wherein conducting wiring can be formed by a dual damascene method, wherein the step of removing the excess materials is selected from the group consisting of planarization by:

chemical mechanical polish (CMP), milling, ion milling, and/or etching.

28. The method of claim 22, in which a electroplating copper ring with pin-like extrusions is positioned over and in contact with the substrate, such that pin-like extrusions cover the alignment marks in kerf areas of said substrate protecting the alignment marks, during a layer of copper deposition by ECP-Cu electrochemical plating of copper, while allowing the layer of copper to plate over the exposed portions of the copper seed layer.

29. The method of claim 22, wherein the layer of dielectric is selected from the group consisting of:

silicon oxide, silicon dioxide, phosphosilicate glass (PSG), fluoro-silicate glass (FSG), deposited by low pressure chemical vapor deposition (LPCVD), a pressure of about 5 Torr, with gases SiH₄ and O₂, and film thickness from 4,000 to 10,000 Angstroms.

30. The method of claim 22, wherein the patterned conducting layer consists of conductively doped polysilicon.

31. The method of claim 22, wherein multilevel conducting structures are fabricated by relating steps (C) through (h).