High-pressure anneal process for integrated circuits

• US 6,492,285 B1
• Filed: 08/31/2000
• Issued: 12/10/2002
• Est. Priority Date: 01/22/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lane, Richard H., Wald, Phillip G.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/652,970
• Time in Patent Office: 831 Days
• Field of Search: 438/396, 438/398, 438/795, 438/796, 438/797, 438/54
• US Class Current: 438/795
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: Y10S 438/904 Charge carrier lifetime control
• CPC Class Codes: Y10S 438/908 Utilizing cluster apparatus

Abstract

This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Claims

1. A method of building a semiconductor device, comprising:

providing a silicon-containing portion of said semiconductor device, said semiconductor device having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device;

performing a fabrication step in relation to a silicon-containing portion of said semiconductor device having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device;

allowing an undesirable effect relating to said silicon-containing portion of said semiconductor device having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device to result from said fabrication step; and

countering at least in part said undesirable effect with an introduction of a high-pressure hydrogen gas to said semiconductor device having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device.

2. The method in claim 1, wherein:

said performing a fabrication step comprises implanting an ion into said semiconductor device; and

said allowing an undesirable effect comprises allowing damage of a crystalline structure of said silicon-containing portion.

3. The method in claim 1, wherein said performing a fabrication step comprises performing a plasma process.

4. The method in claim 3, wherein:

said performing a plasma process comprises depositing silicon dioxide through plasma-enhanced chemical vapor deposition; and

said allowing an undesirable effect comprises allowing said silicon dioxide to trap an electron.

5. The method in claim 3, wherein:

said performing a plasma process comprises plasma etching; and

said allowing an undesirable effect comprises allowing a formation of a dangling bond associated with said silicon-containing portion.

6. The method in claim 5, wherein said plasma etching comprises plasma etching a silicon substrate.

7. The method in claim 5, wherein said plasma etching comprises plasma etching a polycrystalline silicon layer.