Semiconductor integrated circuit device with pad impedance adjustment mechanism

• US 6,492,707 B1
• Filed: 12/21/1998
• Issued: 12/10/2002
• Est. Priority Date: 12/22/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoneya, Kazuhide, Kaku, Mariko
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/217,338
• Time in Patent Office: 1,450 Days
• Field of Search: 257/532, 257/536, 257/691, 257/699, 257/531, 257/533, 257/784, 257/277
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate 11, and pads 13 stacked thereon via an insulation film 12. A particular pad 13a is connected to a signal wiring 17a formed in a bus line region 17, and a capacitor-forming conductor 14 behaving as an impedance adjusting conductor is formed to surround the pad 13a. A source line conductor 15 is made in a space between the pad 13a and the capacitor-forming conductor 14 to encircle the capacitor-forming conductor 14. Therefore, the pad capacitance can be increased by using the space around the pad 13a, other signal wirings 17b and any others formed in the bus line region 17 are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Claims

1. A semiconductor integrated circuit device including semiconductor elements, signal wirings and pads each formed on a semiconductor substrate so as to connect one of said semiconductor elements to one of said signal wirings and to connect said signal wiring to one of said pads, comprising:

a capacitor-forming conductor made in a top layer, arranged around said pad to surround said pad and connected to said pad; and

a first capacitance-coupling conductor made in the top layer between said pad and said capacitor-forming conductor and brought into capacitance coupling with said pad and said capacitor-forming conductor, respectively,

wherein said semiconductor integrated circuit device further comprises a second capacitance-coupling conductor made in the top layer outside said capacitor-forming conductor and brought into capacitance coupling with said capacitor-forming conductor, and said first and second capacitance-coupling conductors are connected to each other, and

said first capacitance-coupling conductor, said capacitor-forming conductor and said second capacitance-coupling conductor are arranged around said pad in an order from inner side to outer side,

said first capacitance-coupling conductor having a first cut section and a second cut section,

said capacitor-forming conductor having a third cut section and said second capacitance-coupling conductor having a fourth cut section,

said second cut section, said third cut section and said fourth cut section being arranged in line,

said pad having a connecting conductor and an outer line connecting conductor, both of which protruding in a radial pattern, respectively,

said connecting conductor being arranged in said first cut section and connecting said pad to said capacitor-forming conductor,

said outer line connecting conductor being arranged in said second, third and fourth cut sections and extending to the outer side of said second capacitance-coupling conductor,

wherein one end of said second cut section of said first capacitance-coupling conductor and one end of said fourth cut section of said second capacitance-coupling conductor being connected to each other through said third cut section,

and the other end of said second cut section of said first capacitance-coupling conductor and the other end of said second capacitance-coupling conductor being connected to each other through said third cut section.

2. The semiconductor integrated circuit device according to claim 1, wherein said first and second capacitance-coupling conductors are connected to a power source line of a lower voltage.

3. The semiconductor integrated circuit device according to claim 1, which has a multi-layered structure including a first layer as the bottom layer, an Nth layer as the top layer, and an insulation film between every two vertically adjacent layers, said Nth layer including said capacitor-forming conductor of the top layer and said first and second capacitance-coupling conductors of the top layer, each of (N−

1)th to first layers having said capacitor-forming conductor for a lower layer and said first and second capacitance-coupling conductors for the lower layer, every two layers vertically adjacent to each other having patterns of said capacitor-forming conductors and said capacitance-coupling conductors inverted from each other so as to confront the pattern of said capacitor-forming conductor of a Pth layer with said capacitance-coupling conductors of a (P−

1)th layer that is vertically adjacent to said Pth layer via said insulation film and to confront said capacitance-coupling conductors of the Pth layer with said capacitor-forming conductor of the (P−

1)th layer via said insulation film, said capacitor-forming conductors of vertically adjacent two of said layers being connected to each other, and said capacitance-coupling conductors of vertically adjacent two of said layers being connected to each other.

4. A semiconductor integrated circuit device comprising a semiconductor substrate having a plurality of elements, signal wirings connecting these elements, a plurality of pads for connecting one or more of the signal wirings to one or more external pins formed on said semiconductor substrate, and

at least one impedance adjusting conductor pattern made to surround one of said pads and connected to said pad, wherein said impedance adjusting conductor pattern is a capacitor-forming conductor, and a first power source line conductor is inserted in a space between said capacitor-forming conductor and said one of said pads, which first power source line conductor is capacitance-coupled with said capacitor-forming conductor and said pad,

wherein the semiconductor integrated circuit device further comprises a second power source line conductor arranged outside of said capacitor-forming conductor and in capacitance coupling with said capacitor-forming conductor, and said first an second power source line conductors are connected, and

wherein combination patterns of said power capacitor-forming conductor and said first and second power source line conductors are made in each layer, adjacent combination patterns being formed via each insulation layer, patterns of said capacitor-forming conductors and said first and second power source line conductors being inverted between adjacent layers, said capacitor-forming conductors of different layers being connected to each other, said first power source line conductors and second power source line conductors of different layers being connected to each other, respectively, and said capacitor-forming conductor of each layer being brought into capacitance coupling with said first and second power source line conductors of horizontally and vertically adjacent layers.

5. A semiconductor integrated circuit device comprising a semiconductor substrate having a plurality of elements, signal wirings connecting these elements, a plurality of pads for connecting one or more of the signal wirings to one or more external pins formed on said semiconductor substrate, and

at least one impedance adjusting conductor pattern made to surround one of said pads and connected to said pad, wherein said impedance adjusting conductor pattern is a capacitor-forming conductor, and a first power source line conductor is inserted in a space between said capacitor-forming conductor and said one of said pads, which first power source line conductor is capacitance-coupled with said capacitor-forming conductor and said pad,

wherein the semiconductor integrated circuit device further comprises a second power source line conductor arranged outside of said capacitor-forming conductor and in capacitance coupling with said capacitor-forming conductor, and said first an second power source line conductors are connected, and

wherein the semiconductor integrated circuit device further comprises a plurality of layers each forming said impedance adjusting conductor pattern via an insulation film such that the value of impedance adjustment is controlled by making or not making contacts between said impedance adjusting patterns in different layers.