Programmable logic device with highly routable interconnect

• US 6,492,834 B1
• Filed: 02/01/2001
• Issued: 12/10/2002
• Est. Priority Date: 04/05/1996
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Veenstra, Kerry S., Lytle, Craig S.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/687,215
• Time in Patent Office: 677 Days
• Field of Search: 326/39, 326/37, 326/40, 326/41, 326/47, 326/38
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (200) comprises an input multiplexer region (504), logic elements (300), input-output pins (516), and output multiplexer region (508).

Claims

1. A logic block for an integrated circuit comprising:

a plurality of logic elements configurable to implement logical functions;

a first stage of a Clos network programmably coupling outputs of the plurality of logic elements and a plurality of first programmable conductors to outputs of the first stage;

a second stage of a Clos network programmably coupling the first stage to outputs of the second stage through a plurality of second programmable conductors, wherein the second stage does not have fan-out; and

a third stage of a Clos network programmably coupling the second stage and outputs of the plurality of logic elements to the plurality of first programmable conductors and the plurality of logic elements.

2. The integrated circuit of claim 1, wherein said logic block further comprises:

an input multiplexer region to programmably couple a plurality of input multiplexer region inputs to a plurality of input multiplexer region outputs, wherein a plurality of the input multiplexer region inputs are coupled to the first plurality of conductors and a plurality of the input multiplexer region outputs are coupled to the second plurality of conductors,

wherein a plurality of the input multiplexer region outputs are coupled to inputs of the configurable logic elements.

3. The integrated circuit of claim 2, wherein the configurable logic elements comprise outputs coupled to a plurality of the input multiplexer region inputs.

4. The integrated circuit of claim 2, wherein said logic block further comprises:

an output multiplexer region to programmably couple a plurality of output multiplexer region inputs to a plurality of output multiplexer region outputs, wherein a plurality of the output multiplexer region inputs are coupled to the second plurality of conductors and a plurality of the output multiplexer region outputs are coupled to the first plurality of conductors,

wherein a plurality of outputs of the configurable logic elements are coupled to a plurality of the inputs of the output multiplexer region.

5. An integrated circuit comprising:

a first stage of a Clos network having inputs and outputs, the first stage programmably coupled to a plurality of logic elements and programmable interconnection resources;

a second stage of a Clos network having inputs and outputs, the second stage programmably coupled to the first stage and the programmable interconnection resources, wherein the second stage does not have fan out; and

a third stage of a Clos network, the third stage programmably coupled to the second stage, the plurality of logic elements, and the programmable interconnection resources.

6. An integrated circuit comprising:

a plurality of logic blocks, wherein a logic array block comprises a plurality of configurable logic elements; and

a routing structure, coupled to the plurality of logic blocks and the plurality of configurable logic elements, the routing structure implementing a Clos network having provable routability to route inputs and outputs of the logic blocks and the configurable logic elements.

7. The integrated circuit of claim 6, wherein the routing structure comprises:

a first plurality of conductors, each of which extends along a first dimension of a two-dimensional array of the logic blocks; and

a second plurality of conductors, each of which extends along a second dimension of the two-dimensional array, the second plurality of conductors programmably coupled to the first plurality of conductors.

8. The integrated circuit of claim 6, wherein the logic block further comprises:

an input multiplexer resource for programmably coupling a plurality of first signal conductors to the configurable logic elements and a first signal plurality of second signal conductors, wherein the plurality of first signal conductors are programmably coupled to the plurality of second signal conductors.

9. The integrated circuit of claim 6, wherein the logic block further comprises:

an output multiplexer resource for programmably coupling the configurable logic elements and a plurality of conductors of the routing structure to a second plurality of conductors of the routing structure.

10. The integrated circuit of claim 6, wherein the routing structure comprises a plurality of first conductors and a plurality of second conductors, and the first and second conductors are programmably coupled, and the logic block further comprises:

an input multiplexer region programmably coupling a plurality of input multiplexer region inputs to a plurality of input multiplexer region outputs, wherein the input multiplexer region outputs are coupled to inputs of the configurable logic elements; and

an output multiplexer region, programmably coupling a plurality of output multiplexer region inputs to a plurality of output multiplexer region outputs, wherein outputs of the configurable logic elements are coupled to the output multiplexer region inputs.

11. The integrated circuit of claim 10, wherein outputs of the configurable logic elements are coupled to the input multiplexer region inputs.

12. The integrated circuit of claim 10, wherein the input multiplexer region outputs are coupled to the second conductors.

13. The integrated circuit of claim 10, wherein the first conductors are coupled to the input multiplexer region inputs.

14. The integrated circuit of claim 10, wherein the second conductors are coupled to the output multiplexer region inputs.

15. The integrated circuit of claim 10, wherein the output multiplexer region outputs are coupled to the first conductors.

16. The integrated circuit of claim 10, wherein the configurable logic elements are coupled through the input multiplexer region or output multiplexer region to the first or second conductors.

17. The integrated circuit of claim 10, wherein the input multiplexer region inputs are coupled to the first conductor and the input multiplexer region outputs are coupled to the second conductors, and the output multiplexer region inputs are coupled to the second conductors and the output multiplexer region outputs are coupled to the first conductors.

18. The integrated circuit of claim 10, further comprising:

a plurality of pads, coupled to the input multiplexer region outputs.

19. The integrated circuit of claim 10, further comprising:

a plurality of pads, coupled to the output multiplexer region inputs.

20. The integrated circuit of claim 10, further comprising:

a plurality of input/output pads, coupled to the input multiplexer region outputs and output multiplexer region inputs.

21. The integrated circuit of claim 6, wherein the integrated circuit is a programmable logic device.

22. The integrated circuit of claim 6, wherein a configurable logic elements comprises a function generator to provide a logical function of a number of variables.