Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same

• US 6,493,048 B1
• Filed: 10/20/1999
• Issued: 12/10/2002
• Est. Priority Date: 10/21/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kong, Hyang-Shik, Baek, Bum-Kee, Kim, Dai-Moe
• Primary Examiner(s): Dudek, James A.
• Application Number:
  US09/421,478
• Time in Patent Office: 1,147 Days
• Field of Search: 349/43, 257/59, 257/72, 438/30
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

Disclosed is a simplified manufacturing method for liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on an insulating substrate. Next, a gate insulating layer covering the gate wire, a semiconductor layer, an ohmic contact layer, and a data conductive layer are sequentially deposited, and a photoresist pattern is formed on the data conductive layer. Following this step, the data conductive layer, using the photoresist pattern as an etch mask, is etched to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, the photoresist pattern is reflowed to cover the portion between the source electrode and the drain electrode, and a portion of the ohmic contact layer adjacent to a periphery of the data wire. Subsequently, portions of the ohmic contact layer and the semiconductor layer, which are not covered by the photoresist pattern, are etched, and the photoresist pattern is removed. Next, a portion of the ohmic contact layer, which is not covered by the data wire, is etched to expose a portion of the semiconductor layer between the source electrode and the drain electrode that is a channel portion of a thin film transistor. Finally, a protection layer, a pixel electrode, a redundant gate pad and a redundant data pad are formed.

Claims

1. A thin film transistor array panel for a liquid crystal display, comprising:

a gate wire formed on an insulating substrate and including a gate line and a gate electrode connected to the gate line;

a gate insulating layer covering the gate wire;

a semiconductor layer formed on the gate insulating layer;

an ohmic contact layer formed on the semiconductor layer;

a data wire including a data line intersecting the gate line, a source electrode connected to the data line and extending to the gate electrode, and a drain electrode located opposite to the source electrode with respect to the gate electrode, the data wire being formed on the ohmic contact layer and having the same layout as the ohmic contact layer;

a protection layer formed on the data wire and the semiconductor layer, and having a first contact hole exposing the drain electrode; and

a pixel electrode connected to the drain electrode through the first contact hole,

wherein a portion of the semiconductor layer on the gate line between adjacent data lines is divided, and

wherein peripheries of the gate insulating layer, the semiconductor layer, and the protection layer are substantially in an identical shape.

2. The thin film transistor array panel of claim 1, wherein the gate wire further includes a gate pad that is connected to and receives a signal from an external circuit, and the data wire further includes a data pad that is connected to and receives a signal from an external circuit, and

wherein the protection layer, the semiconductor layer and the gate insulating layer have a second contact hole and a third contact hole respectively exposing the gate pad and the data pad.

3. The thin film transistor array panel of claim 2, wherein the gate wire has a single-layered or multi-layered structure of aluminum, aluminum alloy, chrome, molybdenum, or molybdenum alloy.