Method and apparatus for performing speculative memory fills into a microprocessor

• US 6,493,802 B1
• Filed: 06/18/1998
• Issued: 12/10/2002
• Est. Priority Date: 06/18/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Kessler, Richard E., Keller, James B., Razdan, Rahul
• Primary Examiner(s): Peikari, Behzad James
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/099,396
• Time in Patent Office: 1,636 Days
• Field of Search: 711/144, 711/204, 711/213, 711/141, 711/145, 712/233, 712/234, 712/235, 712/236, 712/237, 712/238, 712/239, 712/240, 712/23
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/507 using speculative control

Abstract

According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

Claims

1. A method of speculatively filling a cache within a multiprocessor system, the system including a main memory coupled to a plurality of processors having a plurality of caches, comprising the steps of:

determining an address which identifies information located in the main memory, the address also identifying one or more versions of the information located in one or more of the plurality of caches, such address being determined to fill a designated cache with the information;

starting a process of filling the designated cache with the information located in the main memory;

locating one or more other versions of the information identified by the address in the plurality of caches; and

determining validity of the information located in the main memory after locating the one or more other versions of the information, the initiation of the process of filling the designated cache with the information located in the main memory occurring in time before the time of determination of the validity of the information located in main memory.

2. The method of claim 1, further comprising:

canceling the process of filling the designated cache after determining the validity of the information located in the main memory to be invalid.

3. The method of claim 1, wherein:

the process of filling the designated cache has a primer stage wherein a pipeline associated with the filling process is prepared for delivery of the information located in the main memory followed by a delivery stage wherein the information located in the main memory is delivered to the designated cache, and further comprising the step of;

canceling the process of filling the designated cache upon determination that the information located in the main memory is invalid before the information located in the main memory is delivered to the designated cache in the delivery stage.

4. The method of claim 1, wherein:

the validity of the information located in the main memory is invalid if one of the other versions of the information is a more recent version than the information located in the main memory.

5. The method of claim 1, wherein:

the validity of the information located in the main memory is determined to be one of invalid and valid based upon a cache protocol.

6. The method of claim 1, wherein:

the validity of the information located in the main memory is valid if the information located in the main memory is more recent than the other versions of the information.

7. The method of claim 1, further comprising:

completing the process of filling the designated cache without interruption after determining the validity of the information in the main memory to be valid.

8. A computing apparatus, for use within a computer system having a main memory and the computing apparatus connectable to a cache, comprising:

address circuitry for presenting an address to the main memory;

cache fill circuitry for receiving information from the main memory corresponding to the address and for speculatively filling a section of the cache with the information; and

validation circuitry for receiving a validation signal having a value indicating whether the main memory information is valid or invalid, the cache fill circuitry initiating a speculative fill of the cache with the main memory information before the validation circuitry receives the validation signal.

9. The computing apparatus of claim 8, wherein:

the computing apparatus further includes the cache.

10. The computing apparatus of claim 8, wherein:

the cache is located external to the computing apparatus.

11. The computing apparatus of claim 8, further comprising:

cache fill abort circuitry for canceling the filling of the section of the cache with the main memory information if the value of the validation signal indicates the main memory information is invalid, or for continuing the filling of the section of cache if the value of the validation signal indicates the main memory information is valid, the value of the validation signal being determined at a point in time after the point in time the cache fill circuitry begins filling the cache with information, the cache fill thereby being speculative.

12. The computing apparatus of claim 11, wherein:

the cache fill circuitry is configured as a pipeline, and includes;

a data setup stage for preparing the main memory information for delivery to the cache; and

a data delivery stage for receiving the main memory information from the data setup stage and delivering the main memory information to the cache, wherein if the value of the validation signal indicates the main memory information is invalid, the process of filling the cache is canceled by the cache fill abort circuitry before the information is received by the information delivery stage.

13. The computing apparatus of claim 8, further comprising:

a memory controller for receiving the address from the address circuitry, locating the main memory information corresponding to the address and providing the main memory information to the cache fill circuitry.

14. The computing apparatus of claim 8, wherein:

the memory controller sets the value of the validation signal to indicate whether the main memory information is invalid or valid based upon a cache protocol.

15. The computing apparatus of claim 8, wherein:

the memory controller sets the value of the validation signal to indicate the main memory information is invalid if the main memory information is not a most recent version of information.

16. A multiprocessor system, comprising:

a main memory configured to store information;

a memory controller, coupled to the main memory; and

a plurality of processors, each processor coupled to the memory controller and including;

a cache;

a system port configured to receive main memory information from the memory controller;

cache fill circuitry for filling a section of the cache with the main memory information;

validation circuitry for receiving a validation signal having a value indicating whether the main memory information is valid or invalid; and

cache fill abort circuitry for canceling the filling of the section of the cache if the value of the validation signal indicates the main memory information is invalid, the value of the validation signal being determined at a point in time after the point in time when the cache fill circuitry begins the process of filling the cache with the main memory information, the cache fill thereby being speculative.

17. The multiprocessor system of claim 16, wherein:

the memory controller produces the main memory information by retrieving it from the main memory.

18. The multiprocessor system of claim 16, wherein:

the memory controller generates the validation signal.

19. The multiprocessor system of claim 16, wherein:

the memory controller generates the validation signal by setting the value of the validation signal to invalid if a more recent copy of the information than the main memory information is located in one of the other caches, or setting the value of the validation signal to valid if the copy of the information in memory is the most recent copy.

20. A computer system, comprising:

a memory reference unit for selecting an address identifying a selected section of information in a memory;

an address bus for supplying an external system with the address for the selected section of information;

an information bus for receiving the selected section of information from the external system in response to the address;

a cache for storing a plurality of sections of information from the memory;

a validation pin for receiving a validation signal indicating whether the selected section of information is valid or invalid according to a cache protocol; and

cache fill circuitry for filling one of the sections of the cache with the selected section of information, the cache fill process being initiated before determination of the validation signal.

21. The computer system according to claim 20, further comprising:

cache fill abort circuitry for canceling the filling of the selected section of the cache if the validation signal indicates the information is invalid, the validation signal being determined at a point in time after the point in time when the cache fill circuitry begins filling the cache with information, the cache fill thereby being speculative.