Updating flash blocks

• US 6,493,807 B1
• Filed: 07/01/1999
• Issued: 12/10/2002
• Est. Priority Date: 07/01/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Martwick, Andrew W.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US09/346,240
• Time in Patent Office: 1,258 Days
• Field of Search: 711/103, 711/156, 711/106, 711/144, 711/145, 711/152, 711/155, 711/163
• US Class Current: 711/163
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

The present invention is a system and method for updating memory. The contents of a first storage location in a plurality of storage locations are first copied to a second storage location in the plurality of storage locations. A signal indicating that a read operation accessing the first storage location is non-operational, is issued. The contents of the first storage location are erased. A signal indicating that a read operation accessing the first storage location is operational, is then issued.

Claims

1. A system for updating memory comprising:

a block-writable memory;

a processor coupled to said memory, the processor to execute instruction sequences;

wherein the instruction sequences, when executed, cause the processor to;

(a) copy contents of a first storage location in the memory to a second storage location in the memory;

(b) update the contents of the first storage location by writing updated contents to the first storage location;

(c) issue a signal indicating that a read operation accessing the first storage location is non-operational while the contents of the first storage location are being updated; and

(d) issue a signal indicating that a read operation accessing the first storage location is operational after the contents of the first storage location have been updated.

2. The system of claim 1, further comprising a storage element coupled to the processor and the memory, the storage element having a first value indicating that a read operation accessing the first storage location is non-operational, and a second value indicating that a read operation accessing the first storage location is operational.

3. The system of claim 2, wherein in (c), the instruction sequences further cause the processor to assign the first value to the storage element;

and wherein in (d), the instruction sequences further cause the processor to assign the second value to the storage element.

4. The system of claim 1, wherein the block-writable memory comprises flash memory.

5. The system of claim 1, wherein the first and second storage locations are adjacent storage locations.

6. A method comprising:

(a) copying the contents of a first storage location in a memory to a second storage location in the memory;

(b) updating the contents of the first storage location by writing updated contents to the first storage location;

(c) issuing a signal indicating that a read operation accessing the first storage location is non-operational while the contents of the first storage location are being updated; and

(d) issuing a signal indicating that a read operation accessing the first storage location is operational after the contents of the first storage location have been updated.

7. The method of claim 6, wherein (c) further comprises assigning a first value to a storage element indicating that a read operation accessing the first storage location is non-operational;

and wherein (d), further comprises assigning a second value to the storage element indicating that a read operation accessing the first storage location is operational.

8. The method of claim 6, wherein in (a), the memory comprises flash memory.

9. The method of claim 8, wherein the first and second storage locations are adjacent storage locations.

10. A computer program product, comprising:

a computer usable medium having computer program code embodied therein for updating a memory in a processor-based system, the computer program product having;

(a) computer readable program code for copying the contents of a first storage location in a memory to a second storage location in the memory;

(b) computer readable program code for updating the contents of the first storage location by writing updated contents to the first storage location;

(c) computer readable program code for issuing a signal indicating that a read operation accessing the first storage location is non-operational while the contents of the first storage location are being updated; and

(d) computer readable program code for issuing a signal indicating that a read operation accessing the first storage location is operational after the contents of the first storage location have been updated.

11. The computer program product of claim 10, the computer readable program code in (c) is further for assigning a first value to a storage element indicating that a read operation accessing the first storage location is non-operational;

and the computer readable program code in (d) is further for assigning a second value to the storage element indicating that a read operation accessing the first storage location is operational.

12. The computer program product of claim 10, wherein in (a), the memory comprises flash memory.

13. The computer program product of claim 10, wherein the first and second storage locations are adjacent storage locations.

14. The computer program product of claim 13, wherein the first storage location is a top flash memory block.

15. The computer program product of claim 12, wherein the computer program code in (c) is further for updating the contents of the first storage location.