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Maintaining order of write operations in a multiprocessor for memory consistency

  • US 6,493,809 B1
  • Filed: 01/28/2000
  • Issued: 12/10/2002
  • Est. Priority Date: 01/28/2000
  • Status: Expired due to Fees
First Claim
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1. In a multiprocessor system having a number of interconnected processor nodes each containing one or more caches, a method of invalidating cache lines on different nodes linked in a sharing list, the method comprising:

  • from a node at the head of the list, sending an invalidate request to a succeeding node on the list, the invalidate request for invalidating a cache line on the succeeding node; and

    in response to the invalidate request, issuing on the succeeding node an invalidate acknowledgement before actually invalidating the cache line.

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