Flexible cache architecture using modular arrays

• US 6,493,855 B1
• Filed: 02/18/2000
• Issued: 12/10/2002
• Est. Priority Date: 02/18/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Weiss, Donald R, Naffziger, Samuel D
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/507,498
• Time in Patent Office: 1,026 Days
• Field of Search: 716/1-14, 714/710, 365/230, 365/200
• US Class Current: 716/119
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure

Abstract

A system and method which implement a memory component of an integrated circuit as multiple, relatively small sub-arrays of memory to enable great flexibility in organizing memory within the integrated circuit are provided. In a preferred embodiment, the memory component of an integrated circuit is implemented as multiple, relatively small sub-arrays of memory, which enable a designer great flexibility in arranging such sub-arrays within an integrated circuit. Also, in a preferred embodiment, the memory component of an integrated circuit is implemented as multiple memory sub-arrays that are each independent. For example, in a preferred embodiment, each memory sub-array comprises its own decode circuitry for decoding memory addresses that are being requested to be accessed by an instruction, and each memory sub-array comprises its own I/O circuitry. In one implementation of a preferred embodiment, each of the independent memory sub-arrays implemented in an integrated circuit comprises no more than approximately five percent of the total memory implemented on the integrated circuit. In another implementation, each of the independent memory sub-arrays on an integrated circuit is no larger than approximately the average size of other non-memory components implemented on the integrated circuit. Additionally, in further implementation, the memory component of an integrated circuit comprises at least a 20 independent memory sub-arrays. Therefore, in a preferred embodiment, each independent sub-array is relatively small in size to enable great flexibility in organizing the memory on an integrated circuit. Furthermore, because each sub-array is independent, greater flexibility is available in repairing defects through redundancy.

Claims

1. A method of implementing a flexible memory architecture within an integrated circuit, said method comprising:

establishing at least 20 independent sub-arrays of memory within an integrated circuit, wherein each of said independent sub-arrays of memory includes its own decode circuitry for decoding a requested address and its own I/O circuitry;

establishing at least one of said independent sub-arrays of memory as a redundant sub-array of memory, wherein said at least one redundant sub-array of memory is usable to effectively repair a defect within at least one other of said independent sub-arrays of memory; and

distributing said independent sub-arrays around a core of said integrated circuit that comprises an irregularly shaped boundary, wherein said independent sub-arrays are distributed about said irregularly shaped boundary of said core in a manner that manages white space present on said integrated circuit in a desired manner.

2. The method of claim 1 wherein each of said independent sub-arrays have dimensions that are no larger in size than 33 percent of the corresponding dimensions of said core of said integrated circuit.

3. The method of claim 2 wherein said core is a CPU core.

4. The method of claim 1 wherein each of said independent sub-arrays of memory is no larger than approximately the average size of individual functional units included in said core of said integrated circuit.

5. The method of claim 1 wherein each of said independent sub-arrays of memory is physically arid electrically independent of every other one of said independent sub-arrays of memory.

6. The method of claim 1 further including the step of:

routing data from a defective independent sub-array of memory to said redundant sub-array of memory in order to effectively repair said defective independent sub-array of memory.

7. The method of claim 6 wherein said routing data step enables repairing at least one defect selected from the group consisting of:

memory cell defect, decode circuitry defect, and input/output circuitry defect.

16. The method of claim 1 wherein said sub-arrays are distributed to form a memory array having an irregularly shaped boundary.

17. The method of claim 16 wherein said memory array comprises at least one row of sub-arrays that has more sub-arrays than at least one other row.

18. The method of claim 16 wherein said memory array comprises at least one column of sub-arrays that has more sub-arrays than at least one other column.

8. An integrated circuit comprising:

a core comprising a plurality of non-memory components; and

a memory component that is implemented as multiple independent memory sub-arrays that are each no larger in size than approximately the average size of said plurality of non-memory components, wherein said multiple independent memory sub-arrays form a memory array having an irregularly shaped boundary.

9. The integrated circuit of claim 8 wherein each of said independent memory sub-arrays includes no more than approximately five percent of said memory component.

10. The integrated circuit of claim 8 wherein said multiple independent memory sub-arrays are organized within said integrated circuit in a manner that minimizes the amount of white space in said integrated circuit.

11. The integrated circuit of claim 8 wherein said plurality of non-memory components include at least one execution unit of a processor, and wherein said memory component includes cache for said processor.

14. The integrated circuit of claim 8 wherein each of said multiple independent memory sub-arrays includes its own decode circuitry for decoding a requested address and its own I/O circuitry.

12. A computer system comprising:

a core that comprises a processor that executes instructions, said core comprising a width and a length; and

a cache structure accessible by said processor to satisfy memory access requests, wherein said cache structure includes multiple independent sub-arrays of memory that each includes no more than five percent of said cache structure and that each arc no wider than 33 percent of said width of said core and are no longer than 33 percent of said length of said core, wherein said multiple independent sub-arrays of memory form a memory array having an irregularly shaped boundary.

13. The computer system of claim 12 further including an integrated circuit that includes said processor and said cache structure, wherein each of said independent sub-arrays of memory comprises no more than five percent of said cache structure of said integrated circuit.

15. The computer system of claim 12 wherein each of said multiple independent sub-arrays of memory includes its own decode circuitry for decoding a requested address and its own I/O circuitry.