CMOS imager with a self-aligned buried contact
First Claim
1. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
- providing a substrate including at least one transistor and at least one isolation region;
forming a protective layer over said substrate;
selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact.
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Abstract
An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.
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Citations
28 Claims
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1. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
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providing a substrate including at least one transistor and at least one isolation region;
forming a protective layer over said substrate;
selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region; and
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification
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- Resources
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Current AssigneeAptina Imaging Corporation (ON Semiconductor Corporation)
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Original AssigneeMicron Technology, Inc.
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InventorsRhodes, Howard E.
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Primary Examiner(s)Nguyen, Viet Q.
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Assistant Examiner(s)Nhu, David
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Application NumberUS09/715,076Time in Patent Office757 DaysField of Search438/48, 438/60, 438/197, 438/207, 438/229, 438/311, 438/381, 438/579, 438/672, 438/674, 438/675, 438/680, 438/687, 438/755, 438/597US Class Current438/579CPC Class CodesH01L 27/14601 Structural or functional de...H01L 27/14636 Interconnect structures
