Post passivation interconnection schemes on top of the IC chips
First Claim
1. A method of forming a post passivation interconnection, comprising:
- forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate;
forming one or more ESD circuits formed in and on said semiconductor substrate;
a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric;
depositing a passivation layer over said fine line metallization system;
forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin.
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Accused Products
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
23 Claims
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1. A method of forming a post passivation interconnection, comprising:
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forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate;
forming one or more ESD circuits formed in and on said semiconductor substrate;
a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric;
depositing a passivation layer over said fine line metallization system;
forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming a post passivation interconnection, comprising:
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forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate;
forming one or more ESD circuits in and on said semiconductor substrate;
forming a fine line metallization system over said semiconductor substrate in one or more thin layers of dielectric;
depositing a passivation layer over said fine line metallization system;
forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a power or ground distribution network for a power or ground input, respectively, and wherein said thick, wide metallization system is connected to said one or more internal circuits, and to at least one off-chip contact pin. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of forming a post passivation interconnection, comprising:
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forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate;
forming a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric;
depositing a passivation layer over said fine line metallization system;
forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits. - View Dependent Claims (20, 21, 22, 23)
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Specification