Semiconductor device having diode for input protection circuit of MOS structure device

• US 6,495,863 B2
• Filed: 06/19/2001
• Issued: 12/17/2002
• Est. Priority Date: 10/31/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Ryoden Semiconductor System Engineering Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Ryoden Semiconductor System Engineering Corporation
• Inventors: Narazaki, Atsushi
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): Brock, II, Paul E
• Application Number:
  US09/883,201
• Publication Number:
  US 20020050602A1
• Time in Patent Office: 546 Days
• Field of Search: 257/106, 257/199, 257/481, 257/551, 257/603-606, 257/618, 257/622, 257/654, 257/653
• US Class Current: 257/106
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12035 Zener diode
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Claims

1. A semiconductor device comprising:

a base layer; and

a diode arranged on an upper surface of said base layer, wherein

said diode comprises;

a plurality of semiconductor regions extending in a first direction respectively and successively forming p-n junctions in a second direction perpendicular to said first direction,

the conductivity type of a first semiconductor region located on the side of a first end in said second direction among said plurality of semiconductor regions of said diode is equal to the conductivity type of a second semiconductor region located on the side of a second end opposed to said first end, and

the interface between said base layer and said diode in said upper surface of said base layer comprises;

a plurality of groove portions having a depth in a third direction perpendicular to said first direction and said second direction, extending in said second direction and successively arranged in said first direction.

2. The semiconductor device according to claim 1, wherein

at least one of said plurality of semiconductor regions of said diode comprises:

an irregular portion having an irregular shape defined by said plurality of groove portions of said interface.

3. The semiconductor device according to claim 1, wherein

at least one of said plurality of semiconductor regions of said diode comprises:

an upper surface having a flat portion opposed to a bottom surface of each of said plurality of groove portions of said interface in said third direction.

4. The semiconductor device according to claim 1, wherein

said base layer comprises:

a base semiconductor layer of a prescribed conductivity type, and

an insulator film arranged on an upper surface of said base semiconductor layer, and

said insulator film comprises;

an upper surface opposed to an interface between said base semiconductor layer and said insulator film in said third direction and corresponding to said interface between said base layer and said diode.

5. The semiconductor device according to claim 4, wherein

each of said plurality of groove portions is defined as a first groove portion, and

said interface between said base semiconductor layer and said insulator film comprises a plurality of second groove portions each opposed to said first groove portion.

6. The semiconductor device according to claim 5, wherein

a first thickness of said insulator film arranged on a portion of said interface between said base semiconductor layer and said insulator film held between two adjacent second groove portions among said plurality of second groove portions in said third direction is larger than a second thickness of said insulator film arranged on a bottom surface of each of said plurality of second groove portions in said third direction.

7. The semiconductor device according to claim 4, wherein

said prescribed conductivity type of said base semiconductor layer is a first conductivity type, and

said base layer further comprises:

a plurality of semiconductor well regions of a second conductivity type extending from a portion located under a bottom surface of each of said plurality of groove portions in said interface between said base semiconductor layer and said insulator film into said base semiconductor layer.

8. The semiconductor device according to claim 1, further comprising:

a MOS transistor structure, comprising a gate electrode and a main electrode, arranged on a second region in said upper surface of said base layer when defining a portion of said upper surface of said base layer provided with said diode as a first region, wherein

said first semiconductor region is electrically connected with said gate electrode, and

said second semiconductor region is electrically connected with said main electrode.