Ferroelectric memory device having a protective layer

• US 6,495,879 B1
• Filed: 11/22/1999
• Issued: 12/17/2002
• Est. Priority Date: 11/30/1998
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Kobayashi, Sota
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Doan, Theresa T.
• Application Number:
  US09/447,069
• Time in Patent Office: 1,121 Days
• Field of Search: 257/71, 257/68, 257/295, 257/296, 257/303, 257/306, 257/307, 257/308, 257/309, 257/310, 257/311, 257/312, 257/313, 257/532, 257/632, 257/639, 257/640, 257/646, 438/3, 438/238, 438/240, 438/250, 438/373
• US Class Current: 257/310
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A ferroelectric memory device includes an array of memory cells each having a cell transistor and a ferroelectric capacitor, an insulator film overlying the ferroelectric capacitor and including SiN_x or SiO_xN_y, and a protective layer interposed between the insulator film and the ferroelectric capacitor. The ferroelectric capacitor is protected by a protective layer against degradation of storage and programming characteristics which may be caused by the insulator film. The protective layer includes Ir, IrO₂, Ru, RuO₂ or Al₂O₃. The ferroelectric capacitor is also protected against water by the insulator film overlying the first protective layer.

Claims

1. A ferroelectric memory device comprising:

a plurality of memory cells arranged in an array of memory cells each having a cell transistor and a ferroelectric capacitor formed on a semiconductor substrate;

a peripheral circuit;

an interconnection structure for connecting said cell transistor, said ferroelectric capacitor and said peripheral circuit to store data in each of said memory cells, said ferroelectric capacitor including a bottom electrode, a ferroelectric film and a top electrode, said interconnection structure including a first interconnect layer in contact with said top electrode;

an interlayer dielectric film formed on said first interconnect layer;

an insulator film overlying said interlayer dielectric film and including at least one of SiN_x and SiO_xN_y; and

a protective layer disposed between said interlayer dielectric film and said insulator film, said protective layer including at least one of Ir, IrO₂, Ru, RuO₂, and having a higher modulus of elasticity than said interconnect layer.

2. The ferroelectric memory device as defined in claim 1, wherein said protective layer includes consecutively an IrO₂ film and an Ir film as viewed from the bottom.

3. The ferroelectric memory device as defined in claim 1, wherein said protective layer includes consecutively a RuO₂ film and a Ru film as viewed from the bottom.

4. The ferroelectric memory device as defined in claim 1, said protective layer is removed in an area for said peripheral circuit.

5. The ferroelectric memory device as defined in claim 1, wherein the top electrode on the ferroelectric film includes an IrO₂ film in contact with the ferroelectric film and at least one of an Ir and Pt film on the IrO₂ film.