System for testing integrated circuit devices

• US 6,496,027 B1
• Filed: 08/21/1997
• Issued: 12/17/2002
• Est. Priority Date: 08/21/1997
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Micron Technology, Inc.
• Inventors: Wong, Victor, Zheng, Hua, Siek, David D., Sher, Joseph C., Vo, Huy Thanh, Heel, Nicholas Van
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US08/916,994
• Time in Patent Office: 1,944 Days
• Field of Search: 324/763, 324/765, 324/158.1, 365/201, 365/189.09, 365/207
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence

Abstract

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

Claims

1. A system for producing an internal voltage for an integrated circuit device, said system comprising:

a test mode enable circuit adapted for producing a plurality of test signals;

a reference'"'"'signal generator circuit, including;

a voltage generating circuit for producing a voltage;

a control circuit coupled to said voltage generating circuit and to said test mode enable circuit,

wherein said control circuit is adapted for adjusting the voltage produced by the voltage generating circuit by receiving the plurality of test signals and providing corresponding enabling signals to the voltage generator circuit;

wherein each test signal represents a value to which the voltage produced by said voltage generating circuit is to be adjusted; and

wherein said control circuit includes a programmable circuit adapted to be programmed for causing said voltage generating circuit to maintain the voltage at the value to which the voltage has been adjusted, and wherein said voltage generating circuit, said test mode enable circuit, and said control circuit are fabricated in the integrated circuit device.

2. A system for producing test voltages for use in testing an integrated circuit device, comprising:

a test mode enable circuit adapted for producing two or more test signals;

a voltage generating circuit comprising a resistive voltage divider network; and

a control circuit coupled to the voltage generating circuit and to the test mode enable circuit,

wherein the control circuit includes;

at least one test mode circuit for receiving the two or more test signals provided by the test mode enable circuit and for providing at least one test mode output signal;

at least one programmable circuit for providing at least one programmable test output signal; and

at least one logic circuit for receiving the at least one test mode output signal from the at least one test mode circuit, for receiving the at least one programmable test output signal from the at least one programmable circuit, and for providing test vector signals to the voltage generating circuit,

wherein the control circuit is adapted for incrementally adjusting the voltage by a plurality of voltage increments,

wherein each voltage increment corresponds to one of the test signals, and

wherein the control circuit comprises two or more bypass devices adapted to adjust the magnitude of the voltage by selectively bypassing resistances of the voltage divider network.

3. A system for producing test voltage for use in testing an integrated circuit device, comprising:

a test mode enable circuit adapted for producing two or more test signals;

a voltage generating circuit-adapted for producing and maintaining a bias voltage for the integrated circuit device; and

a control circuit coupled to the voltage generating circuit and the test mode enable circuit, wherein;

the control circuit is adapted for incrementally adjusting the bias voltage by a plurality of voltage increments;

each voltage increment corresponds to one of the test signals;

the control circuit includes a programmable circuit;

the programmable circuit includes at least one logic device that is programmable to cause the programmable circuit to provide an output signal indicating an adjusted value for the bias voltage; and

the output signal causes the voltage generating circuit to maintain the bias voltage at a value to which it has been adjusted.

4. The system of claim 3, wherein the programmable logic device comprises an anti-fuse device.

5. A system for producing test voltages for use in testing an integrated circuit device, comprising:

a microcontroller;

a test mode enable circuit coupled to the microcontroller, wherein the test mode enable circuit produces test vectors in response to receiving a signal from the microcontroller;

a control circuit coupled to the test mode enable circuit; and

a voltage generator coupled to the control circuit, wherein;

the voltage generator produces a predetermined voltage; and

the control circuit increments the voltage to one of a plurality of voltage increments, wherein each of the plurality of voltage increments corresponds to one of the test vectors.

6. The system of claim 5, wherein the microcontroller provides coded address signals to the test mode enable circuit and each of the coded address signals corresponds to one of the plurality of voltage increments.

7. A system for producing test voltage for use in testing an integrated circuit device, comprising:

a test mode enable circuit adapted for producing two or more test signals;

a voltage generating circuit adapted for producing and maintaining a bias voltage for the integrated circuit device; and

a control circuit coupled to the test mode enable circuit, wherein;

the control circuit is adapted for incrementally adjusting the bias voltage by a plurality of voltage increments; and

each voltage increment corresponds to one of the test signals.

8. The system of claim 7, wherein:

the voltage generating circuit includes a fixed reference circuit; and

the control circuit overrides the fixed reference circuit in response to the test signals.

9. The system of claim 7, wherein the control circuit comprises:

a first circuit device responsive to a first one of the test signals to cause the voltage generating circuit to increase the bias voltage to a first increased adjusted value;

a second circuit device responsive to a second one of the test signals to cause the voltage generating circuit to increase the bias voltage to a second increased adjusted value;

a third circuit device responsive to a third one of the test signals to cause the voltage generating circuit to decrease the bias voltage to a first decreased adjusted value; and

a fourth circuit device responsive to a fourth one of the test signals to cause the voltage generating circuit to decrease the bias voltage to a second decreased adjusted value.

10. A system for producing test voltages for use in testing an integrated circuit device, comprising:

a microcontroller;

a test mode enable circuit coupled to the microcontroller, wherein the test mode enable circuit produces test vectors in response to receiving a signal from the microcontroller;

a control circuit coupled to the test mode enable circuit; and

a voltage generator coupled to the control circuit, including;

a voltage producing circuit adapted for producing a bias voltage for the integrated circuit device, wherein the control circuit increments the voltage to one of a plurality of voltage increments, and wherein each of the plurality of voltage increments corresponds to one of the test vectors; and

a regulating circuit coupled to the voltage producing circuit and adapted for maintaining the bias voltage.

11. The system of claim 10, wherein the voltage producing circuit comprises an oscillator and a charge pump.

12. The system of claim 10, wherein the regulating circuit includes a fixed reference circuit that is overridden by the control circuit in response to the test vectors.

13. The system of claim 10, wherein the control circuit includes:

at least one device adapted for increasing the bias voltage to at least one increased voltage increment in response to at least one of the test vectors; and

at least one device adapted for decreasing the bias voltage to at least one decreased voltage increment in response to at least one of the test vectors.

14. The system of claim 10, wherein the control circuit includes:

a first device adapted for increasing the bias voltage to a first increased voltage increment in response to a first one of the test vectors; and

a second device adapted for increasing the bias voltage to a second increased voltage increment in response to a second one of the test vectors.

15. The system of claim 10, wherein the control circuit includes:

a first device adapted for decreasing the bias voltage to a first decreased voltage increment in response to a first one of the test vectors; and

a second device adapted for decreasing the bias voltage to a second decreased voltage increment in response to a second one of the test vectors.

16. A system for producing test voltages for use in testing an integrated circuit device, said system comprising:

a test mode enable circuit adapted for producing a plurality of test signals; and

a reference signal generator circuit, including;

a voltage generating circuit for producing a voltage at a setpoint value; and

a control circuit coupled to said voltage generating circuit and to said test mode enable circuit,

wherein said control circuit is adapted for incrementally adjusting the voltage by a plurality of voltage increments by receiving the plurality of test signals and providing corresponding enabling signals to the voltage generator circuit, and

wherein each voltage increment corresponds to one of said plurality of test signals, said voltage generating circuit, said test mode enable circuit and said control circuit being fabricated in the integrated circuit device.

17. The system according to claim 16, wherein the integrated circuit device is contained within a package, and wherein said test mode enable circuit is responsive to coded signals that are generated externally of the package of the integrated circuit device and are applied to signal inputs of the integrated circuit device to cause said test mode enable circuit to produce said plurality of test signals.

18. The system according to claim 16, wherein said voltage generating circuit comprises a resistive voltage divider network including a plurality of resistances, and wherein said control circuit comprises a plurality of bypass devices adapted to be selectively enabled to selectively bypass resistances of said voltage divider network to thereby adjust the magnitude of the voltage.

19. The system according to claim 16, wherein said voltage generating circuit includes a voltage producing circuit and a regulating circuit, said voltage producing circuit producing a bias voltage for the integrated circuit device, and said regulating circuit being coupled to said voltage producing circuit for maintaining the bias voltage at the setpoint value, said control circuit being coupled to said regulating circuit for controlling said regulating circuit as a function of the test signals produced by said test mode enable circuit to adjust the voltage produced by said voltage producing circuit while the integrated circuit device is being operated in a test mode.

20. The system according to claim 19, wherein said regulating circuit includes a fixed reference circuit and said control circuit is responsive to the test signals to override said fixed reference circuit.

21. The system according to claim 19, wherein said control circuit includes first and second circuit devices responsive to respective first and second ones of the test signals to cause said regulating circuit to increase the bias voltage to first and second increased adjusted values, respectively, relative to the setpoint value, and third and fourth circuit devices responsive to respective third and fourth ones of the test signals to cause said regulating circuit to decrease the bias voltage to first and second decreased adjusted values, respectively, relative to the setpoint value.

22. The system according to claim 19, wherein said control circuit includes a programmable circuit including at least one logic device that is programmable to cause the programmable circuit to provide an output signal indicating an adjusted value for the bias voltage and causing said regulating circuit to maintain the bias voltage at a value to which it has been adjusted.

23. The system according to claim 22, wherein said programmable logic device comprises an anti-fuse device.