Output sense amplifier for a multibit memory cell

• US 6,496,051 B1
• Filed: 09/06/2001
• Issued: 12/17/2002
• Est. Priority Date: 09/06/2001
• Status: Expired due to Term

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Hsu, Sheng Teng
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US09/947,671
• Time in Patent Office: 467 Days
• Field of Search: 327/51, 327/52, 327/54, 327/108, 327/427, 327/374, 327/376, 327/377, 327/530, 327/389, 327/391, 327/541, 327/543, 326/106, 326/108, 326/83, 326/56-58, 365/205, 365/185.03, 365/185.21, 365/185.18
• US Class Current: 327/427
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A read circuit for a multibit memory cell is provided to convert a multi-level voltage output from the multibit memory cell into the desired number of binary levels. For example, if the multibit memory cell can be programmed to have four resistance levels, which produce four output voltages respectively, the read circuit is provided with two binary outputs. For additional resistance levels, and corresponding voltage levels, additional binary outputs may be provided.

Claims

1. A read circuit for a multibit memory cell, the read circuit comprising:

a) a voltage input;

b) a first bit-sensing amplifier comprising a first input node connected to the voltage input, a first output bitline, and a first source;

c) a second bit-sensing amplifier comprising a second input node connected to the voltage input, a second output bitline, and a second source; and

d) a voltage divider circuit comprising a level adjustment input connected to the first source, a bit input connected through an inverter to the first output bitline, and a divider output connected to the second source.

2. The read circuit of claim 1, wherein the first bit-sensing amplifier is a CMOS inverter.

3. The read circuit of claim 1, wherein the second bit-sensing amplifier is a CMOS inverter.

4. The read circuit of claim 1, wherein the voltage divider circuit is an NMOS voltage divider.

5. The read circuit of claim 1, wherein the voltage divider is a PMOS voltage divider.

6. The read circuit of claim 1, wherein the first output bitline corresponds to the highest level bit, and the second output bitline corresponds to a lower level bit.

7. The read circuit of claim 1, wherein the first source is connected to ground.

8. A read circuit for a multibit memory cell comprising:

a) a voltage input connected from the multibit memory cell to a first CMOS inverter, such that the voltage input is connected to a first gate of a first PMOS transistor and a second gate of a first NMOS transistor, wherein the first CMOS inverter comprises the first PMOS transistor comprising a first source connected to Vcc and a first drain connected to a first bitline output, the first NMOS transistor comprising a second drain connected to the first bitline output and a second source connected to ground;

b) a first divider circuit comprising a first level adjust input connected to the second source, a first bit input connected to the first bitline output through a first inverter, and a first offset output; and

c) wherein the voltage input is also connected from the multibit memory cell to a second CMOS inverter, such that the voltage input is connected to a third gate of a second PMOS transistor and a fourth gate of an second NMOS transistor, wherein the second CMOS inverter comprises the second PMOS transistor comprising a third source connected to Vcc and a third drain connected to a second bitline output, the second NMOS transistor comprising a fourth drain connected to the second bitline output and a forth source connected to the first offset output.

9. The read circuit of claim 8, further comprising:

a) a second divider circuit comprising a second level adjust input connected to the fourth source, a second bit input connected to the second bitline output through a second inverter, and a second offset output; and

b) wherein the voltage input is also connected from the multibit memory cell to a third CMOS inverter, such that the voltage input is connected to a fifth gate of a third PMOS transistor and a sixth gate of a third NMOS transistor, wherein the third CMOS inverter comprises the third PMOS transistor comprising a fifth source connected to Vcc and a fifth drain connected to a third bitline output, the third NMOS transistor comprising a sixth drain connected to the third bitline output and a sixth source connected to the second offset output.

10. The read circuit of claim 8, wherein the first divider circuit comprises series connected FETs, each FET having a FET gate and a FET drain shorted together, such that the first offset output is derived from a connection point between FETs.

11. A read circuit for a multibit memory cell comprising:

a) a first means for sensing an input voltage from the multibit memory cell and providing a first output voltage;

b) a second means for sensing a voltage difference between the input voltage from the multibit memory cell and an offset voltage, and providing a second output voltage; and

c) a means for providing the offset voltage based upon the first output voltage.