Liquid crystal display device

• US 6,496,169 B1
• Filed: 03/22/1999
• Issued: 12/17/2002
• Est. Priority Date: 03/23/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mametsuka, Koji
• Primary Examiner(s): Shankar, Vijay
• Application Number:
  US09/273,764
• Time in Patent Office: 1,366 Days
• Field of Search: 345/98, 345/87, 345/100, 345/94, 345/96, 345/208, 345/209, 345/210, 345/213, 345/99, 345/204
• US Class Current: 345/87
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The present invention is a liquid crystal display device in which liquid crystal pixels are arranged in an active matrix, and the device includes a timing control circuit for driving an active matrix type liquid crystal display device, in which the superimposing time between adjacent shift resistor output signals from the shift resistors connected in series, is detected by the logic circuit, and in the case where the superimposition of signals occurs as the output of a signal of the subsequent shift resist is started during a signal is being outputted from one previous shift resistor, a timing signal for forcibly turning off the output of the previous shift resistor on the basis of a detected signal by the logic circuit when the subsequent shift resistor is turned on, such as to control the switching operation of the switch for driving the liquid crystal device.

Claims

1. A liquid crystal display device comprising:

liquid crystal pixels provided at intersections of scanning lines and signal lines arranged in matrix on an insulation substrate, and connected to the signal lines via transistors; and

a timing control circuit for driving the liquid crystal pixels, wherein said timing control circuit further comprises;

shift registers consisting of a plurality of flip-flop circuits which are connected in cascade, and each serve to transfer a shift pulse to a next stage sequentially in synchronism with a predetermined clock signal, and output pulses from each stage;

pulse-overlap detecting circuits for receiving output pulses from flip-flop circuits adjacent to each other, and generating and outputting inverted logical product signals of these output pulses; and

output circuits, to which output pulses outputted from one of the previous flip-flop circuits of the adjacent flip-flop circuits, and the inverted logical product signal are input, for generating and outputting logical product signals of the output pulses and the inverted logical product signals.

2. A liquid crystal display device according to claim 1, wherein the pulse-overlap detecting circuits are each made of a NAND gate.

3. A liquid crystal display device according to claim 1, wherein the output circuits are each made of an AND gate.

4. A liquid crystal display device according to claim 1, wherein the shift registers, the pulse-overlap detecting circuits and the output circuits are made of thin film transistors.

5. A liquid crystal display device according to claim 1, wherein the liquid crystal pixels, the shift registers, the pulse-overlap detecting circuits and the output circuits are formed on the same insulating substrate.

6. A liquid crystal display device according to claim 4, wherein the thin film transistors are polycrystalline silicon thin film transistors.

7. A liquid crystal display device according to claim 1, further comprising:

a group of analog switches which open/close depending on the logical product signals outputted consecutively from the output circuits; and

video bus lines connected to the analog switches, for transferring video signals to the liquid crystal pixels, wherein the timing control circuit is applied to a signal line drive circuit for driving said plurality of liquid crystal pixels, each made of a pair of a liquid crystal cell and a thin from transistor.

8. A liquid crystal display device according to claim 7, said liquid crystal pixels are driven in units of blocks of a predetermined group, which are defined by said group of analog switches.

9. An array substrate comprising:

transistors provided at intersections of scanning lines and signal lines arranged in matrix on a substrate, and being in contact with the signal lines and the scanning lines;

a signal line drive circuit for applying video signals to the signal lines; and

a timing control circuit formed in the signal line drive circuit, wherein the timing control circuits comprise;

shift registers consisting of a plurality of flip-flop circuits which are connected in cascade, and each serve to transfer a shift pulse to a next stage sequentially in synchronism with a predetermined clock signal, and output output pulses from stages of the flip flop circuits.

pulse-overlap detecting circuits for receiving output pulses from flip-flop circuits adjacent to each other, and generating and outputting inverted logical product signals of these output pulses; and

output circuits to which output pulses outputted from one previous flip-flop circuit of the adjacent flip-flop circuits, and the inverting logical product signal are input, for generating and outputting logical product signals of the output pulses and the inverted logical product signals.

10. The array substrate according to claim 9 wherein the pulse-overlap detecting circuits each comprise a NAND gate.

11. The array substrate according to claim 9, wherein the output circuits each comprise an AND gate.

12. The array substrate according to claim 9, wherein the shift registers, the pulse-overlap detecting circuits and the output circuits comprise thin film transistors.

13. An array substrate according to claim 12, wherein the thin film transistors are polycrystalline silicon thin film transistors.

14. An array substrate according to claim 9, wherein the signal line drive circuit is formed on the substrate, and said array substrate further comprises:

a group of analog switches which open/close depending on the logical product signals outputted consecutively from the output circuits; and

video bus lines connected to the analog switches, for transferring video signals to the pixels.

15. An array substrate according to claim 9, wherein the signal line drive circuit comprises thin film transistors.

16. An array substrate according to claim 15, wherein the thin film transistors are p-ch silicon thin film transistors.

17. An array substrate according to claim 15, wherein thin film transistors which constitute the signal line drive circuit and the transistors are formed on the same substrate in the same laminate structure.

18. An array substrate according to claim 9, wherein the signal line drive circuit is driven in units of blocks of a predetermined group, which are defined by a group of analog switches.

19. A display device comprising:

pixels provided at intersections of scanning lines and signal lines arranged in matrix on a substrate, and connected to the signal lines via transistors;

timing control circuits for driving the pixels, wherein the timing control circuits each comprise;

a shift register portion made of shift registers connected in series, which consist of a plurality of flip-flop circuits which are connected in cascade, and serve to transfer a shift pulse to a next stage sequentially in synchronism with a predetermined clock signal, and output shift register output signals from each stage;

a NAND gate portion for inputting two shift register output signals to each of the shift registers, one for an input side and another for an output side, and outputting an output signal indicating an overlap section of these signals; and

an AND gate portion for inputting the shift register output signals from the shift registers and the output signals from the NAND gate portion, and generating timing control signals which the shift register output signal outputted from the shift register of the previous stage turned off based on output signals from the NAND gate portion when shift register output signals are outputted from the shift register of a next stage while outputting the shift register output signals from the shift register of the previous stage, connected thereto in series, thus sequentially outputting the generating timing control signals.

20. An array substrate comprising:

scanning lines and signal lines arranged in matrix on a substrate;

transistors provided respectively at intersections of the scanning lines and the signal lines, and being in contact with the signal lines and the scanning lines;

a signal line drive circuit for applying video signals to the signal lines; and

a timing control circuit formed in the signal line drive circuit, wherein the timing control circuits further comprises;

shift registers connected in series, and each serve to transfer a shift pulse to a next stage sequentially, and output shift register output signals from stages;

detecting circuits for detecting an overlapping portion of adjacent shift register output signals in synchronism with a leading edge of a shift register output signal of a next stage; and

a plurality of output circuits, to which shift register output signals are input respectively, wherein said output circuits outputs control signals in which the overlapping portion with the shift register output signals of the next stage is removed from the shift register output signals.

21. An array substrate according to claim 20, wherein said plurality of output circuits, to which the shift register output signals of the next stage are input respectively, outputs signals in which the overlapping portion with the shift register output signals of the previous stage are removed from the shift register output signals of the next stage.

22. An array substrate according to claim 20, wherein the detecting circuits each comprise a NAND gate.

23. An array substrate according to claim 20, wherein the output circuits each comprise an AND gate.

24. An array substrate according to claim 20, wherein the shift registers, the detecting circuits and the output circuits comprise thin film transistors.

25. An array substrate according to claim 24, wherein the thin film transistors are polycrystalline silicon thin film transistors.

26. An array substrate according to claim 24, wherein the signal line and the timing control circuit are formed on the same substrate.

27. An array substrate according to claim 20, wherein the signal line drive circuit comprises thin film transistors.

28. An array substrate according to claim 27, wherein the thin film transistors are p-ch silicon thin film transistors.

29. An array substrate according to claim 27, wherein thin film transistors which constitute the signal line drive circuit and the transistors are formed on the same substrate.

30. An array substrate according to claim 20, wherein the signal line drive circuits are driven in units of blocks of a predetermined group.

31. A liquid crystal display device which employs an array substrate according to claim 20, further comprising:

liquid crystal pixels driven by the timing control circuits, and connected to the scanning lines and the signal lines via the transistors.