Modular architecture for image transposition memory using synchronous DRAM

• US 6,496,192 B1
• Filed: 08/05/1999
• Issued: 12/17/2002
• Est. Priority Date: 08/05/1999
• Status: Expired due to Fees

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shreesha, Vasanth, Nasoff, David
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/368,626
• Time in Patent Office: 1,230 Days
• Field of Search: 345/540, 345/539, 345/531, 345/538, 345/534, 345/545, 345/571, 345/564, 345/418, 345/428, 345/427, 345/649, 345/656-659, 358/443, 358/444, 398/441, 398/583, 382/232, 382/293-297, 365/189.01, 365/189.04, 711/100, 711/5, 711/168, 711/157
• US Class Current: 345/540
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: H04N 5/2628 Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory banks are interleaved on the store operation such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency of the memory. Accordingly, consecutive groups of samples may be stored into the alternating memory banks continuously. When image data are read from memory, the memory read operations are not interleaved. To compensate for the set-up latency in the read operations, the controller advances the first read operation for a particular image line or image column into the horizontal or vertical blanking interval by an amount of time equal to the total latency for the line or column. The system includes a first in first out (FIFO) buffer which receives the image data as it is provided from the memory in response to the memory read requests and provides the image data according to the output timing for the transpose memory.

Claims

1. A memory system for transposing picture elements (pixels) of an image, which pixels are received as a first stream of pixels that would generate an image by being scanned across a display in a first direction, to produce a second stream of pixels that would generate the image by being scanned across the display in a second direction orthogonal to the first direction, the memory system comprising:

a memory device having a plurality of memory cells arranged in first and second banks of memory rows so that any of the pixels in a memory row are accessed without set-up latency after the row has been activated and so that memory write operations to the first bank are interleaved with memory write operations to the second bank;

a memory controller, coupled to the memory device and configured to store the first stream of pixels into the memory device as successive groups of pixels so that groups of pixels which contain adjacent pixels in the second direction are stored in corresponding ones of the plurality of memory rows wherein, when the memory controller activates one memory row in the memory device, one of the pixels and a plurality of pixels which are consecutively adjacent, in the second direction, to the one pixel are available for access as a continuous stream, wherein the memory controller is further configured to store consecutive ones of the groups of pixels into alternate ones of the first and second memory banks so that any memory addressing operation for one memory write operation overlaps with the string of the group of pixels from a previous write operation.

2. A memory system according to claim 1, wherein the memory device is an synchronous dynamic random access (SDRAM) memory device.

3. A memory system according to claim 2, wherein:

each memory write operation occurs in response to a memory write command having a read/write bit in a first polarity and each memory read operation occurs in response to a memory read command having the read/write bit in a second polarity, opposite to the first polarity; and

the memory read operations are converted into memory write operations and the memory write operations are converted into memory read operations by inverting the polarity of the read/write bit in each of the commands.

4. A memory system according to claim 1, wherein each scan line of pixels in the second direction includes a blanking interval and an active interval, a number, N, memory rows are accessed to read a single scan line of pixels in the second direction and each row access includes a predetermined set-up latency period, T, wherein, the memory controller is further configured to start a first read operation, for a first memory row of a scan line of pixels in the second direction, during the blanking interval, an amount of time, N*T, before the active interval.

5. A memory system according to claim 4, further including a first in first out (FIFO) buffer which receives the image data as it is provided from the memory in response to the read operations and provides the scan lines of pixels in the second direction continuously, as the second stream of pixels.

6. A memory system according to claim 5, further comprising a further memory device coupled to the memory controller, wherein the memory controller is configured to control the first memory device to perform successive write operations while controlling the second memory device to perform successive read operations and to control the first memory device to perform successive read operations while controlling the second memory device to perform successive write operations.

7. A memory system according to claim 6, wherein each pixel includes 20 bits comprising a 10-bit luminance value and a 10-bit chrominance value and the memory includes a plurality of one-megabit (Mb) by 16-bit SDRAM devices which hold the eight most significant bits (MSBs) of the luminance values and the chrominance values and one four Mb by four-bit SDRAM device which holds the two least significant bits (LSBs) of the luminance and chrominance values.

8. A method for transposing a first stream of picture element (pixel) data, which would form an image by scanning successive lines of the first stream of pixel data in a first direction, to produce a second stream of pixel data which would form the image by scanning finer successive lines of the second stream of pixel data in a second direction orthogonal to the first direction, using a memory which is arranged as first and second banks of memory rows, each of tee pixels in a memory row being accessed essentially without set-up latency once memory row has been activated, the method comprising the steps of:

forming the first stream of pixel data into successive groups of adjacent pixels;

storing successive groups of pixels alternately into the first and second banks of respective memory rows so that any set-up latency for storing one group of pixels in one bank of the memory occurs while pixel data is being stored into the other bank of the memory, wherein the groups of pixels stored in each memory row are consecutively adjacent in the second direction;

accessing one of the memory rows;

accessing a first pixel from the memory row; and

accessing corresponding pixels in all groups of pixels in the memory row to produce the second stream of pixel data.

9. A method according to claim 8, wherein each memory write operation occurs in response to a memory write command having a read/write bit in a first polarity and each memory read operation occurs in response to a memory read command having the read/write bit in a second polarity, opposite to the first polarity and the method further includes the step of converting the memory read operations into memory write operations and the memory write operations into memory read operations by inverting the polarity of the read/write bit in each of the commands.

10. A method according to claim 8, wherein each scan line of pixels in the second direction includes a blanking interval and an active interval, and a number, N, memory rows are accessed to read a single scan line of pixels in the second direction, each memory access operation including a predetermined set-up latency period, T, the step of accessing one of the memory rows including the step of issuing a memory activation command, to start the memory read operation for the one memory row during the blanking interval an amount of time, N*T, before the active interval.

11. A method according to claim 8, further including the step of storing the pixels provided by the one memory row into a first-in-first-out (FGFO) memory device so that pixels provided from multiple memory rows are provided as a continuous stream.