SOI electrostatic discharge protection circuit

• US 6,496,341 B1
• Filed: 07/24/2000
• Issued: 12/17/2002
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tang, Tien-Hao, Chen, Shiao-Shien
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US09/624,169
• Time in Patent Office: 876 Days
• Field of Search: 361/56, 361/58, 361/91.5, 361/98, 361/111, 361/91, 257/357, 257/360, 327/328, 327/306, 327/437, 327/319, 330/264, 330/277, 330/298
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection circuit. The SOI ESD protection circuit has a first and a second diode, a first and a second NMOS transistor and a first and a second PMOS transistor. The input terminal of the first diode is coupled to the bonding pad while the output terminal is coupled to a voltage source. The input terminal of the second diode is coupled to an earth voltage while the output terminal is coupled to the bonding pad. Both the source terminal and the gate terminal of the first NMOS transistor are coupled to the earth voltage. The drain terminal of the first NMOS transistor is coupled to the voltage source. Both the source and the gate terminal of the second NMOS transistor are coupled to the earth voltage. Both the source and the gate terminal of the first PMOS transistor are coupled to the voltage source. The drain terminal of the first PMOS transistor is coupled to the substrate of the first NMOS transistor. Both the source terminal and the gate terminal of the second PMOS transistor are coupled to the voltage source. The drain terminal of the second PMOS transistor is coupled to the earth voltage. The substrate of the second PMOS transistor is coupled to the drain terminal of the second NMOS transistor. The SOI ESD protection circuit utilizes substrate triggering to boost performance and robustness.

Claims

1. A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection circuit, which is installed between a bonding pad and an input buffer and SOI ESD protection circuit is coupled to the input buffer through a voltage source and an earth voltage, the SOI ESD protection circuit comprising:

a first diode, wherein an input terminal is coupled to the bonding pad and an output terminal is coupled to the voltage source;

a second diode, wherein an input terminal is coupled to the earth voltage and an output voltage is coupled to the bonding pad;

a first NMOS transistor, wherein a source terminal and a gate terminal are coupled to the earth voltage and a drain terminal is coupled to the voltage source;

a second NMOS transistor, wherein a source terminal and a gate terminal are coupled to the earth voltage;

a first PMOS transistor, wherein a source terminal and a gate terminal are coupled to the source voltage and a drain terminal is coupled to the substrate of the first NMOS transistor; and

a second PMOS transistor, wherein a source terminal and a gate terminal are coupled to the voltage source, a drain terminal is coupled to the earth voltage and the substrate is coupled to the drain terminal of the second NMOS transistor.

2. The SOI ESD circuit of claim 1, wherein the input buffer comprises an NMOS transistor and a PMOS transistor serially connected together.