Nonvolatile semiconductor memory device for storing multivalued data
First Claim
Patent Images
1. A method for programming a semiconductor memory device comprising:
- loading a second data to a first latch circuit when data of a memory cell has been changed according to a first data;
loading the first data readout from the memory cell to a second latch circuit;
writing the second data latched in the first latch circuit to the memory cell;
verifying data read from the memory cell to check whether data set to state “
1”
according to the first data has reached state “
2”
according to the second data; and
verifying data read from the memory cell to check whether data set to state “
0”
according to the first data has reached state “
3”
according to the second data.
1 Assignment
0 Petitions
Accused Products
Abstract
A multivalued memory has data of state “0”, state “1”, state “2”, and state “3” whose threshold voltages increase in that order. In a first-page write operation, a memory cell whose data is in state “0” is brought into state “1”. In a second-page write operation, a memory cell whose data is in state “0” is brought into state “3” and a memory cell whose data is in state “1” is brought into state “2”. As a result, in reading the data, the data on the first page can be read in two read operations. Furthermore, the operation of writing the data onto the second page can be made faster, because a high initial write voltage can be used.
66 Citations
7 Claims
-
1. A method for programming a semiconductor memory device comprising:
-
loading a second data to a first latch circuit when data of a memory cell has been changed according to a first data;
loading the first data readout from the memory cell to a second latch circuit;
writing the second data latched in the first latch circuit to the memory cell;
verifying data read from the memory cell to check whether data set to state “
1”
according to the first data has reached state “
2”
according to the second data; and
verifying data read from the memory cell to check whether data set to state “
0”
according to the first data has reached state “
3”
according to the second data.- View Dependent Claims (2, 3)
loading the first data to the first latch circuit;
writing the first data to the memory cell; and
verifying whether data read from the memory cell has reached state “
1”
or still “
0”
,wherein said loading the first data, writing the first data and said verifying being executed prior to loading the second data to the first latch circuit.
-
-
3. The method according to claim 2, wherein said verifying the data comprises reading data from the memory cell by a first potential which is higher than a potential of a read operation.
-
4. A method for programming a semiconductor memory device comprising:
-
loading a first data to a first latch circuit;
writing the first data to a memory cell;
firstly verifying whether data read from the memory cell has reached state “
1”
or still state “
0”
;
loading a second data to the first latch circuit when the data read from the memory cell has changed according to the first data;
loading the first data readout from the memory cell to a second latch circuit;
writing the second data to the memory cell;
secondly verifying data read from the memory cell to check whether data set to state “
1”
according to the first data has reached state “
2”
; and
thirdly verifying data read from the memory cell to check whether data set to state “
0”
according to the first data has reached state “
3”
.- View Dependent Claims (5, 6, 7)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeToshiba Memory Corporation (Kioxia Corporation)
-
Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
-
InventorsTanaka, Tomoharu, Shibata, Noboru
-
Primary Examiner(s)MAI, SON LUU
-
Application NumberUS10/084,509Time in Patent Office292 DaysField of Search365/185.03, 365/185.22, 365/185.24, 365/185.28US Class Current365/185.03CPC Class CodesG11C 11/5621 using charge storage in a f...G11C 11/5628 Programming or writing circ...G11C 11/5642 Sensing or reading circuits...G11C 16/0483 comprising cells having sev...G11C 16/10 Programming or data input c...G11C 16/26 Sensing or reading circuits...G11C 2211/5621 Multilevel programming veri...G11C 2211/5642 Multilevel memory with buff...
