Method and integrated circuit for bit line soft programming (BLISP)

• US 6,496,417 B1
• Filed: 07/27/2000
• Issued: 12/17/2002
• Est. Priority Date: 06/08/1999
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lu, Wen-Pin, Shiau, Tzeng-Huei, Chang, Tso-Ming, Chen, Han Sung, Lin, Yu-Shen, Wan, Ray-Lin
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/601,089
• Time in Patent Office: 873 Days
• Field of Search: 365/185.21, 365/185.3, 365/185.18, 365/185.11, 365/185.2
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

Claims

1. In a floating gate integrated circuit having a first memory array including a plurality of bit lines identified by bit line addresses, the bit lines coupled to floating gate memory cells configured to be programmed and erased, wherein each of the cells has a drain, a source, and a control gate, and wherein the control gates of the cells are in communication with word lines, a method for soft programing floating gate memory cells comprising:

maintaining the word lines at a predetermined word line voltage level;

generating a soft programming pulse having a soft programing voltage level;

selecting a selected bit line in response to a bit line address; and

applying the soft programming voltage level to cells disposed on a subject bit line corresponding to the selected bit line.

2. The soft programming method of claim 1, wherein the subject bit line comprises the selected bit line.

4. The soft programming method of claim 1, wherein:

the selected bit lines have corresponding soft programming flags, and

the method includes, prior to the maintaining, setting the soft program flags for the selected bit lines.

5. The soft programming method of claim 1, wherein the first memory array includes a plurality of blocks, each block having at least one bit line, and wherein prior to the soft programming the method includes erasing cells disposed in the bit lines disposed in blocks having set erase flags.

6. The soft programming method of claim 1, wherein the predetermined word line voltage level is between approximately above ground and 0.5 volts.

7. The soft programming method of claim 1, wherein the soft programming pulse repairs over-erased cells so that the over-erased cells may be reprogrammed absent a previously applied repair verify operation.

8. The soft programming method of claim 1, wherein:

the integrated circuit includes processing resources including a redundancy bit line decoding system;

the selecting includes the decoding system receiving a bit line address input corresponding to the selected bit line; and

the applying includes the processing resources providing a signal to switch on the soft program pulse to the subject bit line.

13. The soft programming method of claim 4, wherein after the applying, the method includes:

determining whether the selected bit line address corresponds to a last address;

responsive to the selected bit line address corresponding to the last address, resetting the soft programming flags for the selected bit lines; and

responsive to the selected bit line address not corresponding to the last address, incrementing the bit line address and repeating the maintaining, generating, selecting, and applying for a next bit line corresponding to the incremented address.

14. The soft programming method of claim 8, wherein at least one cell disposed on each defective bit line remains below a targeted threshold voltage level after a first number of programming cycles.

16. The soft programming method of claim 14, wherein the first number of programming cycles is greater than two.

3. In a floating gate integrated circuit having a first memory array including a plurality of bit lines, the bit lines corresponding to floating gate memory cells configured to be programmed and erased, wherein each of the cells has a drain, a source, and a control gate, and wherein the control gates of the cells are in communication with word lines, a method for soft programming floating gate memory cells comprising:

maintaining the word lines at a predetermined word line voltage level;

generating a soft programming pulse having a soft programming voltage level;

selecting a selected bit line; and

applying the soft programming voltage level to cells disposed on a subject bit line corresponding to the selected bit line, wherein;

the first memory array includes conforming bit lines and defective bit lines;

the selecting includes indicating a bit line type corresponding to the selected bit line, the integrated circuit includes a redundancy system including a second memory array and processing resources, the second memory array having redundant bit lines, the processing resources adapted to perform the indicating, the bit line types including a conforming bit line type and a defective bit line type;

responsive to indicating the conforming bit line type, the subject bit line comprising the selected bit line; and

responsive to indicating the defective bit line type, the subject bit line comprising a subject redundant bit line, the subject redundant bit line logically replacing the selected bit line.

9. The soft programming method of claim 3, wherein at least one of the defective bit lines requires greater charge injection from the soft programming pulse than each of the conforming bit lines to overcome an over-erased condition.

10. The soft programming method of claim 3, wherein the first memory array includes a plurality of blocks, each of the blocks having at least one bit line, and wherein prior to the soft programming the method includes:

erasing cells disposed in conforming bit lines disposed in blocks having set erase flags; and

erasing cells disposed in subject redundant bit lines logically replacing defective bit lines disposed in the blocks having set erase flags.

11. The soft programming method of claim 3, wherein responsive to the indicating of the defective bit line type, the applying includes:

the redundancy system turning off the selected bit line so that the soft programming voltage level is not applied to cells disposed on the selected bit line; and

the redundancy system turning on the subject redundant bit line so that the soft programming voltage level is applied to cells disposed on the subject redundant bit line.

12. The soft programming method of claim 3, wherein:

the bit lines in the first memory array have addresses, the processing resources include a redundancy bit line decoding system having a first set of cells and a logic array, each cell in the first set storing a bit line type indication corresponding to a predetermined bit line address;

the indicating includes;

the redundancy bit line decoding system receiving a bit line address input corresponding to the selected bit line;

the logic array comparing the bit line address input with the bit line type indication of the bit line corresponding to the address input; and

the applying includes;

responsive to the indicating of the defective bit line type, generating a signal to switch off the soft programming pulse for all of the first memory array cells, and to switch on the soft programming pulse for the subject redundant bit line; and

responsive to the indicating of the conforming bit line type, generating a signal to switch on the soft programming pulse to the selected bit line.

15. The soft programming method of claim 12, wherein:

the redundancy bit line decoding system includes an exclusive NOR gate coupled to the bit line address input and the corresponding bit line type indication; and

the applying includes, responsive to the indicating of the defective bit line type, the corresponding exclusive NOR gate toggling on a coupled redundant bit line enable signal.