Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- N (N is a natural number) normal memory cell arrays, each comprising an arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate;
a redundant memory cell array comprising an arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array;
(N+1) erasing bias circuits for applying an erasing bias for erasing data stored in the N normal memory cell arrays and the redundant memory cell array;
N erasing decode circuits for decoding defective address information; and
N redundancy control circuits connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits, wherein the (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data.
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Accused Products
Abstract
A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information. In erasing data, the redundancy control circuits switch the erasing bias circuits so as to inhibit the application of an erasing bias to word and source lines connected to control gates of the normal memory cell array that is replaced by the redundant memory cell array and also inhibit the erasing bias application to those connected to control gates of the unused redundant memory cell array.
28 Citations
17 Claims
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1. A nonvolatile semiconductor memory device comprising:
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N (N is a natural number) normal memory cell arrays, each comprising an arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate;
a redundant memory cell array comprising an arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array;
(N+1) erasing bias circuits for applying an erasing bias for erasing data stored in the N normal memory cell arrays and the redundant memory cell array;
N erasing decode circuits for decoding defective address information; and
N redundancy control circuits connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits, wherein the (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 16, 17)
the second output terminal of one of the adjacent redundancy control circuits and the first output terminal of the other redundancy control circuit are connected in common, each of the N redundancy control circuits stores the defective address information based on the output signal from the erasing decode circuit when the defective address program activation signal is activated, and among the N redundancy control circuits, a redundancy control circuit storing the defective address information controls the next redundancy control circuit so as to switch the terminals for outputting the erasing bias activation signal. -
5. The nonvolatile semiconductor memory device according to claim 1, wherein each of the N redundancy control circuits comprises a nonvolatile memory cell having a control gate and a floating gate to store the defective address information.
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6. The nonvolatile semiconductor memory device according to claim 4, wherein each of the N redundancy control circuits comprises:
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a nonvolatile memory cell having a gate connected to the preceding redundancy control circuit, a source connected to a first power line, and a drain connected to a common node;
a first PMOS transistor having a gate connected to the gate of the nonvolatile memory cell, a source connected to a second power line, and a drain connected to the common node;
a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node;
an inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor;
a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to the common node, a source receiving the defective address information from the erasing decode circuit;
a second NMOS transistor having a gate connected to the output terminal of the inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and
a third NMOS transistor having a gate connected to the input terminal of the inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
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7. The nonvolatile semiconductor memory device according to claim 1, wherein each of the N redundancy control circuits comprises a static memory cell having two inverters to store the defective address information.
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8. The nonvolatile semiconductor memory device according to claim 4, wherein each of the N redundancy control circuits comprises:
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a static memory cell having first and second inverters, wherein an input terminal of the first inverter is connected to an output terminal of the second inverter, while an output terminal of the first inverter is connected to an input terminal of the second inverter;
a first NMOS transistor having a gate receiving the defective address program activation signal, a drain connected to one input/output terminal of the static memory cell, and a source receiving the defective address information from the erasing decode circuit;
a second NMOS transistor having a gate connected to the other input/output terminal of the static memory cell and a source connected to a first power line;
a third NMOS transistor having a gate connected to the preceding redundancy control circuit, a drain connected to a common node, and a source connected to the drain of the second NMOS transistor;
a first PMOS transistor having a gate connected to the gate of the third NMOS transistor, a drain connected to the common node, and a source connected to a second power line;
a second PMOS transistor having a gate connected to the next redundancy control circuit, a source connected to the second power line, and a drain connected to the common node;
a third inverter having an input terminal connected to the common node and an output terminal connected to the gate of the second PMOS transistor;
a fourth NMOS transistor having a gate connected to the output terminal of the third inverter, a source acting as the first output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor; and
a fifth NMOS transistor having a gate connected to the input terminal of the third inverter, a source acting as the second output terminal for switching the erasing bias activation signal to be output, and a drain connected to the source of the first NMOS transistor.
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16. The nonvolatile semiconductor memory device according to claim 1, further comprising an erasing pre-decode circuit comprising an address degeneration circuit for receiving a plurality of erasing address signals and outputting the same number of address degeneration signals as that of the erasing address signals and a multiplex pre-decode circuit for receiving the erasing address signals and the address degeneration signals and outputting a plurality of first and second erasing pre-decode signals,
wherein the erasing decode circuits receive the first and second erasing pre-decode signals from the erasing pre-decode circuit and output erasing decode signals, with which any number of normal memory cell arrays in a plurality of combinations are activated so as to repair a defective address of any one of those normal memory cell arrays. -
17. The nonvolatile semiconductor memory device according to claim 16, wherein the erasing decode circuits are shared in an erasing mode and a program mode, and a number of source lines to be selected in the program as zmode is made smaller than that in the erasing mode by changing the activated address degeneration signals depending on the erasing and program modes.
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9. A nonvolatile semiconductor memory device comprising:
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an erasing pre-decode circuit for receiving a plurality of erasing address signals and outputting a plurality of first and second erasing pre-decode signals, and erasing decode circuits for receiving the first and second erasing pre-decode signals and outputting a plurality of erasing decode signals, wherein the erasing pre-decode circuit comprises an address degeneration circuit for receiving the erasing address signals and outputting the same number of address degeneration signals as that of the erasing address signals and a multiplex pre-decode circuit for receiving the erasing address signals and the address degeneration signals and outputting the erasing pre-decode signals, and a combination of the erasing address signals generates any address degeneration signal so as to degenerate any address of the erasing address signals and thus any of the erasing pre-decode signals are multiplexed, whereby any combination of the erasing address signals activates a desired number of erasing pre-decode signals of the first and second erasing pre-decode signals so that a desired number of erasing decode signals are activated. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification