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Nonvolatile semiconductor memory device

  • US 6,496,427 B2
  • Filed: 08/08/2001
  • Issued: 12/17/2002
  • Est. Priority Date: 08/28/2000
  • Status: Expired due to Fees
First Claim
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1. A nonvolatile semiconductor memory device comprising:

  • N (N is a natural number) normal memory cell arrays, each comprising an arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate;

    a redundant memory cell array comprising an arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array;

    (N+1) erasing bias circuits for applying an erasing bias for erasing data stored in the N normal memory cell arrays and the redundant memory cell array;

    N erasing decode circuits for decoding defective address information; and

    N redundancy control circuits connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits, wherein the (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data.

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