Digital FM receiver employing combined sample-and-hold and integrate-and-dump detectors for improved bit error rates

US 6,496,547 B1
Filed: 11/30/1999
Issued: 12/17/2002
Est. Priority Date: 11/30/1999
Status: Active Grant

First Claim

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1. A machine-implemented method for detecting the bit value corresponding to a data bit-interval of a digital FM receiver limiter-discriminator (LD) output signal, the method comprising the steps of:

(a) integrating the LD output signal over the data bit-interval to produce a first signal representing a first estimate of the corresponding bit value;

(b) producing a first bit detection signal representing a first threshold function of the first signal;

(c) sampling the LD output signal in the data bit-interval to produce a second signal representing a second estimate of the corresponding bit value;

(d) producing a second bit detection signal representing a second threshold function of the second signal; and

(e) combining the first and second bit detection signals to produce a final bit detection signal representing a final estimate of the corresponding bit value.

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Abstract

A narrow-band digital frequency-modulation (FM) limiter-discriminator (LD) receiver with two independent detectors that combine to remove most of the bit errors caused by FM-clicks in an encoded channel. The output of the LD circuit is presented to a sample-and-hold (S&H) detector and to an integrate and dump (I&D) detector. Because the S&H and I&D detector outputs are offset in time by one-half bit and they are not entirely correlated, an error in one does not necessarily imply an error in the other. Using convolutional coding and Viterbi decoding, with threshold-compensation of the I&D detector output and threshold- or envelope-compensation of the S&H detector output, averaging the two compensated detector signals improves the receiver bit error rate (BER) performance by more than 3 dB over the soft-decision thresholded I&D detector alone, which until now was believed to be optimum in the art.

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42 Claims

1. A machine-implemented method for detecting the bit value corresponding to a data bit-interval of a digital FM receiver limiter-discriminator (LD) output signal, the method comprising the steps of:
- (a) integrating the LD output signal over the data bit-interval to produce a first signal representing a first estimate of the corresponding bit value;
  
  (b) producing a first bit detection signal representing a first threshold function of the first signal;
  
  (c) sampling the LD output signal in the data bit-interval to produce a second signal representing a second estimate of the corresponding bit value;
  
  (d) producing a second bit detection signal representing a second threshold function of the second signal; and
  
  (e) combining the first and second bit detection signals to produce a final bit detection signal representing a final estimate of the corresponding bit value.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17)
- - 2. The method of claim 1 wherein the first threshold function comprises a hard decision threshold function.
  - 3. The method of claim 2 wherein the second threshold function comprises a hard decision threshold function.
  - 4. The method of claim 3 wherein L represents a predetermined signal level and the first and second threshold functions are:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 5. The method of claim 2 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 6. The method of claim 1 wherein the first threshold function comprises a soft decision threshold function.
  - 7. The method of claim 6 wherein the second threshold function comprises a soft decision threshold function.
  - 8. The method of claim 7 wherein L represents a predetermined signal level and the first and second threshold functions are:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 9. The method of claim 6 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 10. The method of claim 1 wherein the first signal represents LD output signal phase information at the edges of the data bit-interval.
  - 11. The method of claim 1 wherein the second signal represents LD output signal frequency information at the middle of the data bit-interval.
  - 12. The method of claim 1 wherein the second threshold function comprises a hard decision threshold function.
  - 13. The method of claim 1 wherein the second threshold function comprises a soft decision threshold function.
  - 14. The method of claim 1 wherein the final bit detection signal represents the average of the first and second bit detection signals.
  - 17. The method of claim 14 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$

15. A machine-implemented method for detecting the bit value corresponding to a data bit-interval of the digital FM receiver limiter-discriminator (LD) output signal corresponding to a digital FM receiver LD input signal having an envelope, the method comprising the steps of:
- (a) integrating the LD output signal over the data bit-interval to produce a first signal representing a first estimate of the corresponding bit value;
  
  (b) producing a first bit detection signal representing to a first threshold function of the first signal;
  
  (c) squaring the LD input signal envelope to produce a squared envelope signal;
  
  (d) multiplying the squared envelope signal by the LD output signal to produce a product signal;
  
  (e) sampling the product signal in the data bit-interval to produce a second bit detection signal representing a second estimate of the corresponding bit value; and
  
  (f) combining the first and second bit detection signals to produce a final bit detection signal representing a final estimate of the corresponding bit value.
- View Dependent Claims (16, 18, 19, 20, 21, 22)
- - 16. The method of claim 15 wherein the first threshold function comprises a hard decision threshold function.
  - 18. The method of claim 15 wherein the first threshold function comprises a soft decision threshold function.
  - 19. The method of claim 18 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 20. The method of claim 15 wherein the first signal represents LD output signal phase information at the edges of the data bit-interval.
  - 21. The method of claim 15 wherein the second signal represents LD output signal frequency information at the middle of the data bit-interval.
  - 22. The method of claim 15 wherein the final bit detection signal represents the average of the first and second bit detection signals.

23. A digital FM receiver circuit comprising:
- input means for receiving a digital FM signal representing a plurality of data bit-intervals each having a bit value;
  
  limiter-discriminator (LD) means coupled to the input means for demodulating the digital FM signal to produce a LD output signal having a value over a data bit-interval;
  
  integrate-and-dump (I&
  
  D) detector means coupled to the LD means for integrating the LD output signal over the data bit-interval to produce a first signal representing a first estimate of the corresponding bit value;
  
  first threshold means coupled to the I&
  
  D detector means for producing a first bit detection signal representing a first threshold function of the first signal;
  
  sample-and-hold (S&
  
  H) detector means coupled to the LD means for sampling the LD output signal in the data bit-interval to produce a second signal representing a second estimate of the corresponding bit value;
  
  second threshold means coupled to the S&
  
  H detector means for producing a second bit detection signal representing a second threshold function of the second signal, and combining means coupled to the first and second threshold means for combining the first and second bit detection signals to produce a final bit detection signal representing a final estimate of the corresponding bit value.
- View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
- - 24. The circuit of claim 23 wherein the first threshold function comprises a hard decision threshold function.
  - 25. The circuit of claim 24 wherein the second threshold function comprises a hard decision threshold function.
  - 26. The circuit of claim 25 wherein L represents a predetermined signal level and the first and second threshold functions are:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 27. The circuit of claim 24 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 28. The circuit of claim 23 wherein the first threshold function comprises a soft decision threshold function.
  - 29. The circuit of claim 28 wherein the second threshold function comprises a soft decision threshold function.
  - 30. The circuit of claim 29 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 31. The circuit of claim 28 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 32. The circuit of claim 23 further comprising:
33. The circuit of claim 23 wherein the second threshold function comprises a hard decision threshold function.
34. The circuit of claim 23 wherein the second threshold function comprises a soft decision threshold function.
35. The circuit of claim 23 wherein the final bit detection signal represents the average of the first and second bit detection signals.

36. A digital FM receiver circuit comprising:
- input means for receiving a digital FM signal representing a plurality of data bit-intervals each having a bit value;
  
  limiter-discriminator (LD) means coupled to the input means for demodulating the digital FM signal to produce a LD output signal having a value over a data bit-interval;
  
  integrate-and-dump (I&
  
  D) detector means coupled to the LD means for integrating the LD output signal over the data bit-interval to produce a first signal representing a first estimate of the corresponding bit value;
  
  first threshold means coupled to the I&
  
  D detector means for producing a first bit detection signal representing a first threshold function of the first signal;
  
  envelope squaring means coupled to the input means for squaring the digital FM signal envelope to produce a squared envelope signal;
  
  multiplier means coupled to the envelope squaring means and to the LD means for multiplying the squared envelope signal by the LD output signal to produce a product signal;
  
  sample-and-hold (S&
  
  H) detector means coupled to the multiplier means for sampling the product signal in the data bit-interval to produce a second bit detection signal representing a second estimate of the corresponding bit value; and
  
  combining means coupled to the first and second threshold means for combining the first and second bit detection signals to produce a final bit detection signal representing a final estimate of the corresponding bit value.
- View Dependent Claims (37, 38, 39, 40, 41, 42)
- - 37. The circuit of claim 36 wherein the first threshold function comprises a hard decision threshold function.
  - 38. The circuit of claim 37 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} sgn (z); & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 39. The circuit of claim 36 wherein the first threshold function comprises a soft decision threshold function.
  - 40. The circuit of claim 39 wherein L represents a predetermined signal level and the first threshold function is:
    - $f (z) = {\begin{matrix} z; & \langle z \rangle \leq L \\ 0; & \langle z \rangle > L \end{matrix} .$
  - 41. The circuit of claim 36 further comprising:
42. The circuit of claim 36 wherein the final bit detection signal represents the average of the first and second bit detection signals.

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Current Assignee
Cubic Defense Systems, Inc. (Cubic Corporation)
Original Assignee
Cubic Defense Systems, Inc. (Cubic Corporation)
Inventors
Sorgi, Aladino D., Powell, Robert F.
Primary Examiner(s)
Vo, Don N.

Application Number

US09/451,343
Time in Patent Office

1,113 Days
Field of Search

375/316, 375/337, 375/340, 375/349, 455/42, 455/205, 329/315, 329/327, 329/341
US Class Current

375/316
CPC Class Codes

H04L 1/0059   Convolutional codes

H04L 25/062   Setting decision thresholds...

H04L 27/2275   wherein the carrier recover...

Digital FM receiver employing combined sample-and-hold and integrate-and-dump detectors for improved bit error rates

First Claim

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Digital FM receiver employing combined sample-and-hold and integrate-and-dump detectors for improved bit error rates

First Claim

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Abstract

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42 Claims

Specification

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